diff --git a/svd/patches/_interrupts.yaml b/svd/patches/_interrupts.yaml
new file mode 100644
index 00000000..a6f4e0b2
--- /dev/null
+++ b/svd/patches/_interrupts.yaml
@@ -0,0 +1,464 @@
+# Add additional peripherals not defined elsewhere for grouping of interrupts,
+# these are taken from Table 7: PRO_CPU, APP_CPU Interrupt Configuration, ESP32
+# Technical Reference manual, page 33.
+
+_add:
+  # Processor specific interrupts and exceptions
+  XTENSA:
+    baseAddress: 0
+
+  # Wifi MAC
+  WIFI_MAC:
+    baseAddress: 0
+
+  # Wifi Baseband
+  WIFI_BB:
+    baseAddress: 0
+
+  # Bluetooth MAC
+  BT_MAC:
+    baseAddress: 0
+  
+  # Bluetooth Baseband
+  BT_BB:
+    baseAddress: 0
+
+  # Related to Bluetooth (what is RW?)
+  RW_BT:
+    baseAddress: 0
+  
+  # Related to Bluetooth low energy
+  RW_BLE:
+    baseAddress: 0
+
+  # Ethernet MAC
+  ETH_MAC:
+    baseAddress: 0
+  
+  # SDIO
+  SDIO:
+    baseAddress: 0
+  
+  # Ethernet
+  ETH:
+    baseAddress: 0
+  
+  # Watchdog timer
+  WDT:
+    baseAddress: 0
+
+# Interrupts are defined in order of interrupt value
+
+WIFI_MAC:
+  _add:
+    _interrupts:
+      WIFI_MAC_INTR:
+        description: "interrupt of WiFi MAC, level"
+        value: 0
+
+      WIFI_MAC_NMI:
+        description: "interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI"
+        value: 1
+
+WIFI_BB:
+  _add:
+    _interrupts:
+      WIFI_BB_INTR:
+        description: "interrupt of WiFi BB, level, we can do some calibration"
+        value: 2
+
+BT_MAC:
+  _add:
+    _interrupts:
+      BT_MAC_INTR:
+        description: "will be cancelled"
+        value: 3
+
+BT_BB:
+  _add:
+    _interrupts:
+      BT_BB_INTR:
+        description: "interrupt of BT BB, level"
+        value: 4
+
+      BT_BB_NMI:
+        description: "interrupt of BT BB, NMI, use if BB have bug to fix in NMI"
+        value: 5
+
+RW_BT:
+  _add:
+    _interrupts:    
+      RWBT_INTR:
+        description: "interrupt of RWBT, level"
+        value: 6
+
+RW_BLE:
+  _add:
+    _interrupts:
+      RWBLE_INTR:
+        description: "interrupt of RWBLE, level"
+        value: 7
+
+RW_BT:
+  _add:
+    _interrupts:    
+      RWBT_NMI:
+        description: "interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI"
+        value: 8
+
+RW_BLE:
+  _add:
+    _interrupts:
+      RWBLE_NMI:
+        description: "interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI"
+        value: 9
+
+SLC:
+  _add:
+    _interrupts:
+      SLC0_INTR:
+        description: "interrupt of SLC0, level"
+        value: 10
+
+      SLC1_INTR:
+        description: "interrupt of SLC1, level"
+        value: 11
+
+UHCI0:
+  _add:
+    _interrupts:
+      UHCI0_INTR:
+        description: "interrupt of UHCI0, level"
+        value: 12
+
+UHCI1:
+  _add:
+    _interrupts:
+      UHCI1_INTR:
+        description: "interrupt of UHCI1, level"
+        value: 13
+
+TIMG0:
+  _add:
+    _interrupts:
+      TG0_T0_LEVEL_INTR:
+        description: "interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission"
+        value: 14
+
+      TG0_T1_LEVEL_INTR:
+        description: "interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission"
+        value: 15
+
+      TG0_WDT_LEVEL_INTR:
+        description: "interrupt of TIMER_GROUP0, WATCHDOG, level"
+        value: 16
+
+      TG0_LACT_LEVEL_INTR:
+        description: "interrupt of TIMER_GROUP0, LACT, level"
+        value: 17
+
+TIMG1:
+  _add:
+    _interrupts:
+      TG1_T0_LEVEL_INTR:
+        description: "interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission"
+        value: 18
+    
+      TG1_T1_LEVEL_INTR:
+        description: "interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission"
+        value: 19
+
+      TG1_WDT_LEVEL_INTR:
+        description: "interrupt of TIMER_GROUP1, WATCHDOG, level"
+        value: 20
+    
+      TG1_LACT_LEVEL_INTR:
+        description: "interrupt of TIMER_GROUP1, LACT, level"
+        value: 21
+
+GPIO:
+  _add:
+    _interrupts:
+      GPIO_INTR:
+        description: "interrupt of GPIO, level"
+        value: 22
+
+      GPIO_NMI:
+        description: "interrupt of GPIO, NMI"
+        value: 23
+
+XTENSA:
+  _add:
+    _interrupts:
+      FROM_CPU_INTR0:
+        description: "interrupt0 generated from a CPU, level"
+        value: 24
+
+      FROM_CPU_INTR1:
+        description: "interrupt1 generated from a CPU, level"
+        value: 25
+  
+      FROM_CPU_INTR2:
+        description: "interrupt2 generated from a CPU, level"
+        value: 26
+
+      FROM_CPU_INTR3:
+        description: "interrupt3 generated from a CPU, level"
+        value: 27
+
+SPI0:
+  _add:
+    _interrupts:      
+      SPI0_INTR:
+        description: "interrupt of SPI0, level, SPI0 is for Cache Access, do not use this"
+        value: 28
+
+SPI1:
+  _add:
+    _interrupts:      
+      SPI1_INTR:
+        description: "interrupt of SPI1, level, SPI1 is for flash read/write, do not use this"
+        value: 29
+
+SPI2:
+  _add:
+    _interrupts:      
+      SPI2_INTR:
+        description: "interrupt of SPI2, level"
+        value: 30
+
+SPI3:
+  _add:
+    _interrupts:      
+      SPI3_INTR:
+        description: "interrupt of SPI3, level"
+        value: 31
+
+I2S:
+  _add:
+    _interrupts:      
+      I2S0_INTR:
+        description: "interrupt of I2S0, level"
+        value: 32
+
+      I2S1_INTR:
+        description: "interrupt of I2S1, level"
+        value: 33
+
+UART0:
+  _add:
+    _interrupts:      
+      UART0_INTR:
+        description: "interrupt of UART0, level"
+        value: 34
+
+UART1:
+  _add:
+    _interrupts:      
+      UART1_INTR:
+        description: "interrupt of UART1, level"
+        value: 35
+
+UART2:
+  _add:
+    _interrupts:      
+      UART2_INTR:
+        description: "interrupt of UART2, level"
+        value: 36
+
+SDIO:
+  _add:
+    _interrupts:      
+      SDIO_HOST_INTR:
+        description: "interrupt of SD/SDIO/MMC HOST, level"
+        value: 37
+
+ETH:
+  _add:
+    _interrupts:      
+      ETH_MAC_INTR:
+        description: "interrupt of ethernet mac, level"
+        value: 38
+
+PWM0:
+  _add:
+    _interrupts:      
+      PWM0_INTR:
+        description: "interrupt of PWM0, level, Reserved"
+        value: 39
+
+PWM1:
+  _add:
+    _interrupts:      
+      PWM1_INTR:
+        description: "interrupt of PWM1, level, Reserved"
+        value: 40
+
+PWM2:
+  _add:
+    _interrupts:      
+      PWM2_INTR:
+        description: "interrupt of PWM2, level"
+        value: 41
+      
+PWM3:
+  _add:
+    _interrupts:      
+      PWM3_INTR:
+        description: "interrupt of PWM3, level"
+        value: 42
+
+LEDC:
+  _add:
+    _interrupts:      
+      LEDC_INTR:
+        description: "interrupt of LED PWM, level"
+        value: 43
+      
+EFUSE:
+  _add:
+    _interrupts:      
+      EFUSE_INTR:
+        description: "interrupt of efuse, level, not likely to use"
+        value: 44
+      
+CAN:
+  _add:
+    _interrupts:      
+      CAN_INTR:
+        description: "interrupt of can, level"
+        value: 45
+      
+RTCCNTL:
+  _add:
+    _interrupts:      
+      RTC_CORE_INTR:
+        description: "interrupt of rtc core, level, include rtc watchdog"
+        value: 46
+      
+RMT:
+  _add:
+    _interrupts:      
+      RMT_INTR:
+        description: "interrupt of remote controller, level"
+        value: 47
+
+PCNT:
+  _add:
+    _interrupts:      
+      PCNT_INTR:
+        description: "interrupt of pluse count, level"
+        value: 48
+
+I2C0:
+  _add:
+    _interrupts:      
+      I2C_EXT0_INTR:
+        description: "interrupt of I2C controller0, level"
+        value: 49
+
+I2C1:
+  _add:
+    _interrupts:      
+      I2C_EXT1_INTR:
+        description: "interrupt of I2C controller1, level"
+        value: 50
+
+RSA:
+  _add:
+    _interrupts:      
+      RSA_INTR:
+        description: "interrupt of RSA accelerator, level"
+        value: 51
+
+SPI1:
+  _add:
+    _interrupts:      
+      SPI1_DMA_INTR:
+        description: "interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this"
+        value: 52
+
+SPI2:
+  _add:
+    _interrupts:      
+      SPI2_DMA_INTR:
+        description: "interrupt of SPI2 DMA, level"
+        value: 53
+      
+SPI3:
+  _add:
+    _interrupts:      
+      SPI3_DMA_INTR:
+        description: "interrupt of SPI3 DMA, level"
+        value: 54
+      
+WDT:
+  _add:
+    _interrupts:      
+      WDT_INTR:
+        description: "will be cancelled"
+        value: 55
+
+XTENSA:
+  _add:
+    _interrupts:
+      TIMER1_INTR:
+        description: "will be cancelled"
+        value: 56
+
+      TIMER2_INTR:
+        description: "will be cancelled"
+        value: 57
+
+TIMG0:
+  _add:
+    _interrupts:
+      TG0_T0_EDGE_INTR:
+        description: "interrupt of TIMER_GROUP0, TIMER0, EDGE"
+        value: 58
+      
+      TG0_T1_EDGE_INTR:
+        description: "interrupt of TIMER_GROUP0, TIMER1, EDGE"
+        value: 59
+      
+      TG0_WDT_EDGE_INTR:
+        description: "interrupt of TIMER_GROUP0, WATCH DOG, EDGE"
+        value: 60
+      
+      TG0_LACT_EDGE_INTR:
+        description: "interrupt of TIMER_GROUP0, LACT, EDGE"
+        value: 61
+      
+TIMG1:
+  _add:
+    _interrupts:      
+      TG1_T0_EDGE_INTR:
+        description: "interrupt of TIMER_GROUP1, TIMER0, EDGE"
+        value: 62
+      
+      TG1_T1_EDGE_INTR:
+        description: "interrupt of TIMER_GROUP1, TIMER1, EDGE"
+        value: 63
+      
+      TG1_WDT_EDGE_INTR:
+        description: "interrupt of TIMER_GROUP1, WATCHDOG, EDGE"
+        value: 64
+      
+      TG1_LACT_EDGE_INTR:
+        description: "interrupt of TIMER_GROUP0, LACT, EDGE"
+        value: 65
+
+XTENSA:
+  _add:
+    _interrupts:      
+      MMU_IA_INTR:
+        description: "interrupt of MMU Invalid Access, LEVEL"
+        value: 66
+
+      MPU_IA_INTR:
+        description: "interrupt of MPU Invalid Access, LEVEL"
+        value: 67
+
+      CACHE_IA_INTR:
+        description: "interrupt of Cache Invalid Access, LEVEL"
+        value: 68
diff --git a/svd/patches/esp32.yaml b/svd/patches/esp32.yaml
index 3737fbf1..a7f4c008 100644
--- a/svd/patches/esp32.yaml
+++ b/svd/patches/esp32.yaml
@@ -4,16 +4,7 @@ _svd: ../esp32.base.svd
 _include:
   - "_rename_registers.yaml"
   - "_rename_bitfields.yaml"
-
-# TODO patch in interrupt information
-
-_add:
-  TIMG0:
-    derivedFrom: TIMG
-    baseAddress: "0x3ff5F000"
-  TIMG1:
-    derivedFrom: TIMG
-    baseAddress: "0x3ff60000"
+  - "_interrupts.yaml"
 
 _modify:
   PWM:
@@ -23,20 +14,40 @@ _modify:
   I2C1_EXT:
     name: I2C1
 
+_copy:
+  TIMG0:
+    from: TIMG
+  TIMG1:
+    from: TIMG
+  SPI0:
+    from: SPI
+  SPI1:
+    from: SPI
+  SPI2:
+    from: SPI
+  SPI3:
+    from: SPI
+  PWM0:
+    from: MCPWM
+  PWM1:
+    from: MCPWM
+  PWM2:
+    from: MCPWM
+  PWM3:
+    from: MCPWM
+  I2C0:
+    from: I2C
+  I2C1:
+    from: I2C
+  UHCI0:
+    from: UHCI
+  UHCI1:
+    from: UHCI
+  UART0:
+    from: UART1
 
-_derive:
-  SPI0: SPI
-  SPI1: SPI
-  SPI2: SPI
-  SPI3: SPI
-
-  UHCI0: UHCI
-  UHCI1: UHCI
-
-  PWM0: MCPWM
-  PWM1: MCPWM
-  PWM2: MCPWM
-  PWM3: MCPWM
-
-  I2C0: I2C
-  I2C1: I2C
\ No newline at end of file
+_modify:
+  TIMG0:
+    baseAddress: "0x3ff5F000"
+  TIMG1:
+    baseAddress: "0x3ff60000"