From dd0b18e1eccb8786bcfe0ee7bcf20d988cbc5743 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 16 Feb 2020 20:52:18 -0800 Subject: [PATCH 001/874] [X86] Disable load folding for X86ISD::ADD with 128 as an immediate. It can be turned into a sub with -128 instead as long as the carry flag isn't used. --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 5 +++++ llvm/test/CodeGen/X86/add.ll | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 24d46da80c086..a3d383b0f55de 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -643,6 +643,11 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const { if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB) && (-Imm->getAPIntValue()).isSignedIntN(8)) return false; + + if ((U->getOpcode() == X86ISD::ADD || U->getOpcode() == X86ISD::SUB) && + (-Imm->getAPIntValue()).isSignedIntN(8) && + hasNoCarryFlagUses(SDValue(U, 1))) + return false; } // If the other operand is a TLS address, we should fold it instead. diff --git a/llvm/test/CodeGen/X86/add.ll b/llvm/test/CodeGen/X86/add.ll index 1662562bd013f..9de5645158733 100644 --- a/llvm/test/CodeGen/X86/add.ll +++ b/llvm/test/CodeGen/X86/add.ll @@ -560,8 +560,8 @@ declare void @bar_i64(i64) define void @add_i32_128_flag(i32 %x) { ; X32-LABEL: add_i32_128_flag: ; X32: # %bb.0: # %entry -; X32-NEXT: movl $128, %eax -; X32-NEXT: addl {{[0-9]+}}(%esp), %eax +; X32-NEXT: movl {{[0-9]+}}(%esp), %eax +; X32-NEXT: subl $-128, %eax ; X32-NEXT: je .LBB19_2 ; X32-NEXT: # %bb.1: # %if.then ; X32-NEXT: pushl %eax From 7a551600d1af561e91f7f66210d1ffd588c426fd Mon Sep 17 00:00:00 2001 From: River Riddle Date: Sun, 16 Feb 2020 21:06:56 -0800 Subject: [PATCH 002/874] [mlir] Address post commit feedback of D73590 for SymbolsAndSymbolTables.md --- mlir/docs/SymbolsAndSymbolTables.md | 40 +++++++++++++++-------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/mlir/docs/SymbolsAndSymbolTables.md b/mlir/docs/SymbolsAndSymbolTables.md index 0a026dd502433..f4d5d6b446b88 100644 --- a/mlir/docs/SymbolsAndSymbolTables.md +++ b/mlir/docs/SymbolsAndSymbolTables.md @@ -2,13 +2,13 @@ [TOC] -MLIR is a multi-level representation, with [Regions](LangRef.md#regions) the -multi-level aspect is structural in the IR. A lot of infrastructure within the -compiler is built around this nesting structure, including the processing of -operations within the [pass manager](WritingAPass.md#pass-manager). One -advantage of the MLIR design is that it is able to process operations in -parallel, utilizing multiple threads. This is possible due to a property of the -IR known as [`IsolatedFromAbove`](Traits.md#isolatedfromabove). +With [Regions](LangRef.md#regions), the multi-level aspect of MLIR is structural +in the IR. A lot of infrastructure within the compiler is built around this +nesting structure; including the processing of operations within the +[pass manager](WritingAPass.md#pass-manager). One advantage of the MLIR design +is that it is able to process operations in parallel, utilizing multiple +threads. This is possible due to a property of the IR known as +[`IsolatedFromAbove`](Traits.md#isolatedfromabove). Without this property, any operation could affect or mutate the use-list of operations defined above. Making this thread-safe requires expensive locking in @@ -37,8 +37,10 @@ link, or use, to the symbol. An example of a `Symbol` operation is ### Defining a Symbol -A `Symbol` operation may use the `OpTrait::Symbol` trait, but have the following -properties: +A `Symbol` operation may use the `OpTrait::Symbol` trait to provide the +necessary verification and accessors, but this is not required as some +operations, such as `module`, conditionally define a symbol. `Symbol`s must have +the following properties: * A `StringAttr` attribute named 'SymbolTable::getSymbolAttrName()'(`sym_name`). @@ -57,7 +59,7 @@ Described above are `Symbol`s, which reside within a region of an operation defining a `SymbolTable`. A `SymbolTable` operation provides the container for the [`Symbol`](#symbol) operations. It verifies that all `Symbol` operations have a unique name, and provides facilities for looking up symbols by name. -Operations defining a `SymbolTable` may use the `OpTrait::SymbolTable` trait. +Operations defining a `SymbolTable` must use the `OpTrait::SymbolTable` trait. ### Referencing a Symbol @@ -69,7 +71,7 @@ further resolve to a symbol nested within a different symbol table. When resolving a nested reference, each non-leaf reference must refer to a symbol operation that is also a [symbol table](#symbol-table). -Below is an example of how an operation may reference a symbol operation: +Below is an example of how an operation can reference a symbol operation: ```mlir // This `func` operation defines a symbol named `symbol`. @@ -93,8 +95,8 @@ func @other_symbol() { // Here we define a nested symbol table. References within this operation will // not resolve to any symbols defined above. module { - // Error. We resolve references with respect to the closest parent symbol - // table, so this reference can't be resolved. + // Error. We resolve references with respect to the closest parent operation + // that defines a symbol table, so this reference can't be resolved. "foo.user"() {uses = [@symbol]} : () -> () } @@ -107,7 +109,7 @@ module @module_symbol { // Our `foo.user` operation may refer to the nested symbol, by resolving through // the parent. -"foo.user"() {uses = [@module_symbol::@symbol]} : () -> () +"foo.user"() {uses = [@module_symbol::@nested_symbol]} : () -> () ``` Using an attribute, as opposed to an SSA value, has several benefits: @@ -171,9 +173,9 @@ The following are a few of the utilities provided by the `SymbolTable`: Along with a name, a `Symbol` also has a `visibility` attached to it. The `visibility` of a symbol defines its structural reachability within the IR. A -symbol may have one of the following visibilities: +symbol has one of the following visibilities: -* Public +* Public (Default) - The symbol may be referenced from outside of the visible IR. We cannot assume that all of the uses of this symbol are observable. @@ -196,14 +198,14 @@ module @public_module { // externally; all uses are known to reside within parent regions. func @nested_function() attributes { sym_visibility = "nested" } - // This function cannot be accessed outside of 'public_module' + // This function cannot be accessed outside of 'public_module'. func @private_function() attributes { sym_visibility = "private" } } -// This function can only be accessed from within the top-level module +// This function can only be accessed from within the top-level module. func @private_function() attributes { sym_visibility = "private" } -// This function may be referenced externally +// This function may be referenced externally. func @public_function() "live.user"() {uses = [ From 487fcc8d3de43aabfaeb981eaebeb106398117c4 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Mon, 17 Feb 2020 00:18:01 -0500 Subject: [PATCH 003/874] Fix `-Wpedantic` warning. NFC. --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 8b6097d3a4087..dad8417315051 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -190,7 +190,7 @@ static LegalityPredicate greaterThan(unsigned TypeIdx0, unsigned TypeIdx1) { return Query.Types[TypeIdx0].getSizeInBits() > Query.Types[TypeIdx1].getSizeInBits(); }; -}; +} AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, const GCNTargetMachine &TM) From 1ae05a3c6690cbdf36d1dcdbc852d6c46d10bcb8 Mon Sep 17 00:00:00 2001 From: Kang Zhang Date: Mon, 17 Feb 2020 05:27:36 +0000 Subject: [PATCH 004/874] [NFC][PowerPC] Add a new test case scalar-equal.ll --- llvm/test/CodeGen/PowerPC/scalar-equal.ll | 57 +++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/scalar-equal.ll diff --git a/llvm/test/CodeGen/PowerPC/scalar-equal.ll b/llvm/test/CodeGen/PowerPC/scalar-equal.ll new file mode 100644 index 0000000000000..f1337c614b382 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/scalar-equal.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names --enable-unsafe-fp-math \ +; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \ +; RUN: --enable-no-nans-fp-math \ +; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ +; RUN: --check-prefix=FAST-P8 +; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names --enable-unsafe-fp-math \ +; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \ +; RUN: --enable-no-nans-fp-math \ +; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ +; RUN: --check-prefix=FAST-P9 +; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \ +; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ +; RUN: --check-prefix=NO-FAST-P9 +; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \ +; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ +; RUN: --check-prefix=NO-FAST-P8 + +define double @testoeq(double %a, double %b, double %c, double %d) { +; FAST-P8-LABEL: testoeq: +; FAST-P8: # %bb.0: # %entry +; FAST-P8-NEXT: xscmpudp cr0, f1, f2 +; FAST-P8-NEXT: fmr f1, f3 +; FAST-P8-NEXT: beqlr cr0 +; FAST-P8-NEXT: # %bb.1: # %entry +; FAST-P8-NEXT: fmr f1, f4 +; FAST-P8-NEXT: blr +; +; FAST-P9-LABEL: testoeq: +; FAST-P9: # %bb.0: # %entry +; FAST-P9-NEXT: xssubdp f0, f1, f2 +; FAST-P9-NEXT: fsel f1, f0, f3, f4 +; FAST-P9-NEXT: xsnegdp f0, f0 +; FAST-P9-NEXT: fsel f1, f0, f1, f4 +; FAST-P9-NEXT: blr +; +; NO-FAST-P9-LABEL: testoeq: +; NO-FAST-P9: # %bb.0: # %entry +; NO-FAST-P9-NEXT: xssubdp f0, f1, f2 +; NO-FAST-P9-NEXT: fsel f1, f0, f3, f4 +; NO-FAST-P9-NEXT: xsnegdp f0, f0 +; NO-FAST-P9-NEXT: fsel f1, f0, f1, f4 +; NO-FAST-P9-NEXT: blr +; +; NO-FAST-P8-LABEL: testoeq: +; NO-FAST-P8: # %bb.0: # %entry +; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2 +; NO-FAST-P8-NEXT: fmr f1, f3 +; NO-FAST-P8-NEXT: beqlr cr0 +; NO-FAST-P8-NEXT: # %bb.1: # %entry +; NO-FAST-P8-NEXT: fmr f1, f4 +; NO-FAST-P8-NEXT: blr +entry: + %cmp = fcmp fast oeq double %a, %b + %cond = select fast i1 %cmp, double %c, double %d + ret double %cond +} From 113df90388d8b84ea6af0f30b8696a0139ed7088 Mon Sep 17 00:00:00 2001 From: QingShan Zhang Date: Mon, 17 Feb 2020 05:42:49 +0000 Subject: [PATCH 005/874] [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions We have the InstAlias rules for 32-bit rotate but missing the 64-bit one. Rotate left immediate rotlwi ra,rs,n rlwinm ra,rs,n,0,31 Rotate left rotlw ra,rs,rb rlwnm ra,rs,rb,0,31 Differential Revision: https://reviews.llvm.org/D72676 --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 4 ++++ llvm/test/CodeGen/PowerPC/bperm.ll | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 43431a1e00698..f870194656e0a 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -909,6 +909,10 @@ def ISEL8 : AForm_4<31, 15, } // hasSideEffects = 0 } // End FXU Operations. +def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; +def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; +def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; +def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; //===----------------------------------------------------------------------===// // Load/Store instructions. diff --git a/llvm/test/CodeGen/PowerPC/bperm.ll b/llvm/test/CodeGen/PowerPC/bperm.ll index 2f3118a7f395c..53b19620ec131 100644 --- a/llvm/test/CodeGen/PowerPC/bperm.ll +++ b/llvm/test/CodeGen/PowerPC/bperm.ll @@ -9,7 +9,7 @@ entry: ret i32 %0 ; CHECK-LABEL: @bs4 -; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31 +; CHECK: rotlwi [[REG1:[0-9]+]], 3, 8 ; CHECK: rlwimi [[REG1]], 3, 24, 16, 23 ; CHECK: rlwimi [[REG1]], 3, 24, 0, 7 ; CHECK: mr 3, [[REG1]] From dd8a2013dc1804be1b7d9cffacad2e984300bd22 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sun, 16 Feb 2020 22:34:42 -0800 Subject: [PATCH 006/874] [MC] Delete two unused MCCodePadder functions missed by D71106 --- llvm/include/llvm/MC/MCStreamer.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h index 11f0bdfc4e593..8a447731f6798 100644 --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -803,12 +803,6 @@ class MCStreamer { virtual void emitValueToOffset(const MCExpr *Offset, unsigned char Value, SMLoc Loc); - virtual void - EmitCodePaddingBasicBlockStart(const MCCodePaddingContext &Context) {} - - virtual void - EmitCodePaddingBasicBlockEnd(const MCCodePaddingContext &Context) {} - /// @} /// Switch to a new logical file. This is used to implement the '.file From f4e920720da0b93d4149576b94aa193c97b79633 Mon Sep 17 00:00:00 2001 From: Kang Zhang Date: Mon, 17 Feb 2020 08:34:56 +0000 Subject: [PATCH 007/874] [NFC][PowerPC] Update the test case scalar-equal.ll Modify the command option to add --enable-no-nans-fp-math --- llvm/test/CodeGen/PowerPC/scalar-equal.ll | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/llvm/test/CodeGen/PowerPC/scalar-equal.ll b/llvm/test/CodeGen/PowerPC/scalar-equal.ll index f1337c614b382..5b58d7f3d6e17 100644 --- a/llvm/test/CodeGen/PowerPC/scalar-equal.ll +++ b/llvm/test/CodeGen/PowerPC/scalar-equal.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names --enable-unsafe-fp-math \ ; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \ -; RUN: --enable-no-nans-fp-math \ +; RUN: --enable-no-nans-fp-math --enable-no-infs-fp-math \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ ; RUN: --check-prefix=FAST-P8 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names --enable-unsafe-fp-math \ ; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \ -; RUN: --enable-no-nans-fp-math \ +; RUN: --enable-no-nans-fp-math --enable-no-infs-fp-math \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ ; RUN: --check-prefix=FAST-P9 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \ @@ -19,11 +19,10 @@ define double @testoeq(double %a, double %b, double %c, double %d) { ; FAST-P8-LABEL: testoeq: ; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xscmpudp cr0, f1, f2 -; FAST-P8-NEXT: fmr f1, f3 -; FAST-P8-NEXT: beqlr cr0 -; FAST-P8-NEXT: # %bb.1: # %entry -; FAST-P8-NEXT: fmr f1, f4 +; FAST-P8-NEXT: xssubdp f0, f1, f2 +; FAST-P8-NEXT: xsnegdp f1, f0 +; FAST-P8-NEXT: fsel f0, f0, f3, f4 +; FAST-P8-NEXT: fsel f1, f1, f0, f4 ; FAST-P8-NEXT: blr ; ; FAST-P9-LABEL: testoeq: From cfb29e4a54b051c888cbff8ed100c7dff5e33d58 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Mon, 17 Feb 2020 09:39:06 +0100 Subject: [PATCH 008/874] [lldb] Fix some tests failing with gmodules after change to stdlib.h Commit 82b47b2978405f802a33b00d046e6f18ef6a47be changes the way the stdlib.h header is structured which seems to cause strange lookup failures in the modules build. This updates a few failing tests so that they pass with the new behavior of stdlib.h. See the discussion in https://reviews.llvm.org/rG82b47b2978405f802a33b00d046e6f18ef6a47be --- .../commands/expression/import-std-module/conflicts/main.cpp | 1 + .../test/API/commands/expression/static-initializers/main.cpp | 2 +- lldb/test/API/lang/cpp/operators/main.cpp | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/lldb/test/API/commands/expression/import-std-module/conflicts/main.cpp b/lldb/test/API/commands/expression/import-std-module/conflicts/main.cpp index e49b862a36c6b..ea48c73bc9d5b 100644 --- a/lldb/test/API/commands/expression/import-std-module/conflicts/main.cpp +++ b/lldb/test/API/commands/expression/import-std-module/conflicts/main.cpp @@ -1,5 +1,6 @@ #include #include +#include int main(int argc, char **argv) { std::size_t f = argc; diff --git a/lldb/test/API/commands/expression/static-initializers/main.cpp b/lldb/test/API/commands/expression/static-initializers/main.cpp index 0bcf1eb3edafb..4b0a082d296ec 100644 --- a/lldb/test/API/commands/expression/static-initializers/main.cpp +++ b/lldb/test/API/commands/expression/static-initializers/main.cpp @@ -4,7 +4,7 @@ int counter = 0; void inc_counter() { ++counter; } -void do_abort() { abort(); } +void do_abort() { std::abort(); } int main() { return 0; // break here diff --git a/lldb/test/API/lang/cpp/operators/main.cpp b/lldb/test/API/lang/cpp/operators/main.cpp index 892d0bae42af4..ed1161952bf29 100644 --- a/lldb/test/API/lang/cpp/operators/main.cpp +++ b/lldb/test/API/lang/cpp/operators/main.cpp @@ -4,8 +4,8 @@ int side_effect = 0; struct B { int dummy = 2324; }; struct C { - void *operator new(size_t size) { C* r = ::new C; r->custom_new = true; return r; } - void *operator new[](size_t size) { C* r = static_cast(std::malloc(size)); r->custom_new = true; return r; } + void *operator new(std::size_t size) { C* r = ::new C; r->custom_new = true; return r; } + void *operator new[](std::size_t size) { C* r = static_cast(std::malloc(size)); r->custom_new = true; return r; } void operator delete(void *p) { std::free(p); side_effect = 1; } void operator delete[](void *p) { std::free(p); side_effect = 2; } From 7ae1347fb259c6f5feb92567192c0b1032553c02 Mon Sep 17 00:00:00 2001 From: Sylvestre Ledru Date: Mon, 17 Feb 2020 10:02:11 +0100 Subject: [PATCH 009/874] clang analyzer: Fix the webpage rendering --- clang/www/analyzer/alpha_checks.html | 3 --- 1 file changed, 3 deletions(-) diff --git a/clang/www/analyzer/alpha_checks.html b/clang/www/analyzer/alpha_checks.html index 3d4075e5aaf9c..181ce1b9de591 100644 --- a/clang/www/analyzer/alpha_checks.html +++ b/clang/www/analyzer/alpha_checks.html @@ -1083,9 +1083,6 @@

Non-determinism Alpha Checkers

f(i); } - - -