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jwanggit86jwanggit86
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Rename pseudo insn suffix from _vop3_e64 to _opsel_e64
1 parent 017786d commit 209ff03

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8 files changed

+48
-47
lines changed

8 files changed

+48
-47
lines changed

‎llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -735,9 +735,9 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) {
735735
case AMDGPU::V_ASHRREV_I16_e32:
736736
case AMDGPU::V_LSHLREV_B16_e32:
737737
case AMDGPU::V_LSHRREV_B16_e64:
738-
case AMDGPU::V_LSHRREV_B16_vop3_e64:
738+
case AMDGPU::V_LSHRREV_B16_opsel_e64:
739739
case AMDGPU::V_ASHRREV_I16_e64:
740-
case AMDGPU::V_LSHLREV_B16_vop3_e64:
740+
case AMDGPU::V_LSHLREV_B16_opsel_e64:
741741
case AMDGPU::V_LSHLREV_B16_e64: {
742742
// from: v_lshrrev_b16_e32 v1, 8, v0
743743
// to SDWA src:v0 src_sel:BYTE_1
@@ -760,13 +760,13 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) {
760760
break;
761761

762762
if (Opcode == AMDGPU::V_LSHLREV_B16_e32 ||
763-
Opcode == AMDGPU::V_LSHLREV_B16_vop3_e64 ||
763+
Opcode == AMDGPU::V_LSHLREV_B16_opsel_e64 ||
764764
Opcode == AMDGPU::V_LSHLREV_B16_e64)
765765
return std::make_unique<SDWADstOperand>(Dst, Src1, BYTE_1, UNUSED_PAD);
766766
return std::make_unique<SDWASrcOperand>(
767767
Src1, Dst, BYTE_1, false, false,
768768
Opcode != AMDGPU::V_LSHRREV_B16_e32 &&
769-
Opcode != AMDGPU::V_LSHRREV_B16_vop3_e64 &&
769+
Opcode != AMDGPU::V_LSHRREV_B16_opsel_e64 &&
770770
Opcode != AMDGPU::V_LSHRREV_B16_e64);
771771
break;
772772
}

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -212,7 +212,8 @@ multiclass VOP2Inst_e64_t16<string opName,
212212
let OtherPredicates = [Has16BitInsts], True16Predicate = NotHasTrue16BitInsts in {
213213
defm NAME : VOP2Inst<opName, P, node, revOp>;
214214
let SubtargetPredicate = isGFX10Only in {
215-
def _vop3_e64 : VOP3InstBase <opName#"_vop3", VOP3_Profile<P, VOP3_OPSEL>, node, 1>,
215+
// V_MAX_I16 etc use VOP3 encoding and allow OP_SEL
216+
def _opsel_e64 : VOP3InstBase <opName#"_vop3", VOP3_Profile<P, VOP3_OPSEL>, node, 1>,
216217
Commutable_REV<revOp#"_vop3_e64", !eq(revOp, opName)>;
217218
}
218219
}

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1932,14 +1932,14 @@ defm V_DIV_FIXUP_F16 :
19321932
defm V_ADD_NC_U16 : VOP3OpSel_Real_gfx10<0x303>;
19331933
defm V_SUB_NC_U16 : VOP3OpSel_Real_gfx10<0x304>;
19341934

1935-
defm V_MUL_LO_U16 : VOP3OpSel_Real_gfx10_with_name<0x305, "V_MUL_LO_U16_vop3", "v_mul_lo_u16">;
1936-
defm V_LSHRREV_B16 : VOP3OpSel_Real_gfx10_with_name<0x307, "V_LSHRREV_B16_vop3", "v_lshrrev_b16">;
1937-
defm V_ASHRREV_I16 : VOP3OpSel_Real_gfx10_with_name<0x308, "V_ASHRREV_I16_vop3", "v_ashrrev_i16">;
1938-
defm V_MAX_U16 : VOP3OpSel_Real_gfx10_with_name<0x309, "V_MAX_U16_vop3", "v_max_u16">;
1939-
defm V_MAX_I16 : VOP3OpSel_Real_gfx10_with_name<0x30a, "V_MAX_I16_vop3", "v_max_i16">;
1940-
defm V_MIN_U16 : VOP3OpSel_Real_gfx10_with_name<0x30b, "V_MIN_U16_vop3", "v_min_u16">;
1941-
defm V_MIN_I16 : VOP3OpSel_Real_gfx10_with_name<0x30c, "V_MIN_I16_vop3", "v_min_i16">;
1942-
defm V_LSHLREV_B16 : VOP3OpSel_Real_gfx10_with_name<0x314, "V_LSHLREV_B16_vop3", "v_lshlrev_b16">;
1935+
defm V_MUL_LO_U16 : VOP3OpSel_Real_gfx10_with_name<0x305, "V_MUL_LO_U16_opsel", "v_mul_lo_u16">;
1936+
defm V_LSHRREV_B16 : VOP3OpSel_Real_gfx10_with_name<0x307, "V_LSHRREV_B16_opsel", "v_lshrrev_b16">;
1937+
defm V_ASHRREV_I16 : VOP3OpSel_Real_gfx10_with_name<0x308, "V_ASHRREV_I16_opsel", "v_ashrrev_i16">;
1938+
defm V_MAX_U16 : VOP3OpSel_Real_gfx10_with_name<0x309, "V_MAX_U16_opsel", "v_max_u16">;
1939+
defm V_MAX_I16 : VOP3OpSel_Real_gfx10_with_name<0x30a, "V_MAX_I16_opsel", "v_max_i16">;
1940+
defm V_MIN_U16 : VOP3OpSel_Real_gfx10_with_name<0x30b, "V_MIN_U16_opsel", "v_min_u16">;
1941+
defm V_MIN_I16 : VOP3OpSel_Real_gfx10_with_name<0x30c, "V_MIN_I16_opsel", "v_min_i16">;
1942+
defm V_LSHLREV_B16 : VOP3OpSel_Real_gfx10_with_name<0x314, "V_LSHLREV_B16_opsel", "v_lshlrev_b16">;
19431943
defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>;
19441944
defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>;
19451945

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ body: |
100100
; GFX10-NEXT: {{ $}}
101101
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
102102
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
103-
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
103+
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
104104
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
105105
; GFX11-LABEL: name: ashr_s16_s16_vs
106106
; GFX11: liveins: $sgpr0, $vgpr0
@@ -193,7 +193,7 @@ body: |
193193
; GFX10-NEXT: {{ $}}
194194
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
195195
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
196-
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
196+
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
197197
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
198198
; GFX11-LABEL: name: ashr_s16_s16_vv
199199
; GFX11: liveins: $vgpr0, $vgpr1
@@ -238,7 +238,7 @@ body: |
238238
; GFX10-NEXT: {{ $}}
239239
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
240240
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
241-
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
241+
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
242242
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
243243
; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_ASHRREV_I16_e64_]], implicit $exec
244244
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
@@ -292,7 +292,7 @@ body: |
292292
; GFX10-NEXT: {{ $}}
293293
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
294294
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
295-
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
295+
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
296296
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
297297
; GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
298298
; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_1]], [[V_ASHRREV_I16_e64_]], implicit $exec
@@ -442,7 +442,7 @@ body: |
442442
; GFX10-NEXT: {{ $}}
443443
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
444444
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
445-
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
445+
; GFX10-NEXT: [[V_ASHRREV_I16_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
446446
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ASHRREV_I16_e64_]]
447447
; GFX11-LABEL: name: ashr_s16_s16_sv
448448
; GFX11: liveins: $sgpr0, $vgpr0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ body: |
9898
; GFX10-NEXT: {{ $}}
9999
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
100100
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
101-
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
101+
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
102102
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
103103
; GFX11-LABEL: name: lshr_s16_s16_vs
104104
; GFX11: liveins: $sgpr0, $vgpr0
@@ -191,7 +191,7 @@ body: |
191191
; GFX10-NEXT: {{ $}}
192192
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
193193
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
194-
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
194+
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
195195
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
196196
; GFX11-LABEL: name: lshr_s16_s16_vv
197197
; GFX11: liveins: $vgpr0, $vgpr1
@@ -236,7 +236,7 @@ body: |
236236
; GFX10-NEXT: {{ $}}
237237
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
238238
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
239-
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
239+
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
240240
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
241241
; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_LSHRREV_B16_e64_]], implicit $exec
242242
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
@@ -290,7 +290,7 @@ body: |
290290
; GFX10-NEXT: {{ $}}
291291
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
292292
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
293-
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
293+
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
294294
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
295295
; GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
296296
; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_1]], [[V_LSHRREV_B16_e64_]], implicit $exec
@@ -440,7 +440,7 @@ body: |
440440
; GFX10-NEXT: {{ $}}
441441
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
442442
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
443-
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
443+
; GFX10-NEXT: [[V_LSHRREV_B16_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
444444
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B16_e64_]]
445445
; GFX11-LABEL: name: lshr_s16_s16_sv
446446
; GFX11: liveins: $sgpr0, $vgpr0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -103,9 +103,9 @@ body: |
103103
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
104104
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
105105
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
106-
; GFX10-NEXT: [[V_MAX_I16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I16_vop3_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
106+
; GFX10-NEXT: [[V_MAX_I16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I16_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
107107
; GFX10-NEXT: [[V_MED3_I16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_I16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
108-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_I16_e64_]], implicit [[V_MAX_I16_vop3_e64_]]
108+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_I16_e64_]], implicit [[V_MAX_I16_opsel_e64_]]
109109
;
110110
; GFX11-LABEL: name: smed3_s16_vvv_multiuse0
111111
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
@@ -168,9 +168,9 @@ body: |
168168
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
169169
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
170170
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
171-
; GFX10-NEXT: [[V_MIN_I16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I16_vop3_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
171+
; GFX10-NEXT: [[V_MIN_I16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I16_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
172172
; GFX10-NEXT: [[V_MED3_I16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_I16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
173-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_I16_e64_]], implicit [[V_MIN_I16_vop3_e64_]]
173+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_I16_e64_]], implicit [[V_MIN_I16_opsel_e64_]]
174174
;
175175
; GFX11-LABEL: name: smed3_s16_vvv_multiuse1
176176
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
@@ -234,10 +234,10 @@ body: |
234234
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
235235
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
236236
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
237-
; GFX10-NEXT: [[V_MIN_I16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I16_vop3_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
238-
; GFX10-NEXT: [[V_MAX_I16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I16_vop3_e64 0, [[V_MIN_I16_vop3_e64_]], 0, [[COPY2]], 0, 0, implicit $exec
237+
; GFX10-NEXT: [[V_MIN_I16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I16_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
238+
; GFX10-NEXT: [[V_MAX_I16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I16_opsel_e64 0, [[V_MIN_I16_opsel_e64_]], 0, [[COPY2]], 0, 0, implicit $exec
239239
; GFX10-NEXT: [[V_MED3_I16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_I16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
240-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_I16_e64_]], implicit [[V_MAX_I16_vop3_e64_]]
240+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_I16_e64_]], implicit [[V_MAX_I16_opsel_e64_]]
241241
;
242242
; GFX11-LABEL: name: smed3_s16_vvv_multiuse2
243243
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -103,9 +103,9 @@ body: |
103103
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
104104
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
105105
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
106-
; GFX10-NEXT: [[V_MAX_U16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U16_vop3_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
106+
; GFX10-NEXT: [[V_MAX_U16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U16_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
107107
; GFX10-NEXT: [[V_MED3_U16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
108-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_U16_e64_]], implicit [[V_MAX_U16_vop3_e64_]]
108+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_U16_e64_]], implicit [[V_MAX_U16_opsel_e64_]]
109109
;
110110
; GFX11-LABEL: name: umed3_s16_vvv_multiuse0
111111
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
@@ -168,9 +168,9 @@ body: |
168168
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
169169
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
170170
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
171-
; GFX10-NEXT: [[V_MIN_U16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U16_vop3_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
171+
; GFX10-NEXT: [[V_MIN_U16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U16_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
172172
; GFX10-NEXT: [[V_MED3_U16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
173-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_U16_e64_]], implicit [[V_MIN_U16_vop3_e64_]]
173+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_U16_e64_]], implicit [[V_MIN_U16_opsel_e64_]]
174174
;
175175
; GFX11-LABEL: name: umed3_s16_vvv_multiuse1
176176
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
@@ -234,10 +234,10 @@ body: |
234234
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
235235
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
236236
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
237-
; GFX10-NEXT: [[V_MIN_U16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U16_vop3_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
238-
; GFX10-NEXT: [[V_MAX_U16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U16_vop3_e64 0, [[V_MIN_U16_vop3_e64_]], 0, [[COPY2]], 0, 0, implicit $exec
237+
; GFX10-NEXT: [[V_MIN_U16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U16_opsel_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
238+
; GFX10-NEXT: [[V_MAX_U16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U16_opsel_e64 0, [[V_MIN_U16_opsel_e64_]], 0, [[COPY2]], 0, 0, implicit $exec
239239
; GFX10-NEXT: [[V_MED3_U16_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
240-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_U16_e64_]], implicit [[V_MAX_U16_vop3_e64_]]
240+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MED3_U16_e64_]], implicit [[V_MAX_U16_opsel_e64_]]
241241
;
242242
; GFX11-LABEL: name: umed3_s16_vvv_multiuse2
243243
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -103,8 +103,8 @@ body: |
103103
; GFX10-NEXT: {{ $}}
104104
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
105105
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
106-
; GFX10-NEXT: [[V_LSHLREV_B16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
107-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B16_vop3_e64_]]
106+
; GFX10-NEXT: [[V_LSHLREV_B16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
107+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B16_opsel_e64_]]
108108
;
109109
; GFX11-LABEL: name: shl_s16_s16_vs
110110
; GFX11: liveins: $sgpr0, $vgpr0
@@ -202,8 +202,8 @@ body: |
202202
; GFX10-NEXT: {{ $}}
203203
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
204204
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
205-
; GFX10-NEXT: [[V_LSHLREV_B16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
206-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B16_vop3_e64_]]
205+
; GFX10-NEXT: [[V_LSHLREV_B16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
206+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B16_opsel_e64_]]
207207
;
208208
; GFX11-LABEL: name: shl_s16_s16_vv
209209
; GFX11: liveins: $vgpr0, $vgpr1
@@ -250,9 +250,9 @@ body: |
250250
; GFX10-NEXT: {{ $}}
251251
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
252252
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
253-
; GFX10-NEXT: [[V_LSHLREV_B16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
253+
; GFX10-NEXT: [[V_LSHLREV_B16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
254254
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
255-
; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_LSHLREV_B16_vop3_e64_]], implicit $exec
255+
; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_LSHLREV_B16_opsel_e64_]], implicit $exec
256256
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
257257
;
258258
; GFX11-LABEL: name: shl_s16_s16_vv_zext_to_s32
@@ -307,10 +307,10 @@ body: |
307307
; GFX10-NEXT: {{ $}}
308308
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
309309
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
310-
; GFX10-NEXT: [[V_LSHLREV_B16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
310+
; GFX10-NEXT: [[V_LSHLREV_B16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
311311
; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
312312
; GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
313-
; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_1]], [[V_LSHLREV_B16_vop3_e64_]], implicit $exec
313+
; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_1]], [[V_LSHLREV_B16_opsel_e64_]], implicit $exec
314314
; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
315315
; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1
316316
; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
@@ -466,8 +466,8 @@ body: |
466466
; GFX10-NEXT: {{ $}}
467467
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
468468
; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
469-
; GFX10-NEXT: [[V_LSHLREV_B16_vop3_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_vop3_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
470-
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B16_vop3_e64_]]
469+
; GFX10-NEXT: [[V_LSHLREV_B16_opsel_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B16_opsel_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
470+
; GFX10-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B16_opsel_e64_]]
471471
;
472472
; GFX11-LABEL: name: shl_s16_s16_sv
473473
; GFX11: liveins: $sgpr0, $vgpr0

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