[llvm][ARM] Emit MVE .arch_extension after .fpu directive if it does not include MVE features (#71545)

The floating-point and MVE features together specify the MVE
functionality that is supported on the Cortex-M85 processor. But the FPU
extension for the underlying architecture(armv8.1-m.main) is FPV5 which
does not include MVE-F. So Compiler's -S output and `-save-temps=obj`
loses MVE feature which leads to assembler error. What happening here is
.fpu directive overrides any previously set features by .cpu directive.
Since the the corresponding .fpu generated (.fpu fpv5-d16) does not
include MVE-F, it overrides those features even though it is supported
and set by the .cpu directive. Looks like .fpu is supposed to do this.

In this case, there should be an .arch_extension directive re-enabling
the relevant extensions after .fpu if the goal is to keep these
extensions enabled. GCC also does the same.

So this patch enables the MVE features by emitting the below arch
extension:
  .fpu fpv5-d16
  .arch_extension mve.fp

---------

Co-authored-by: Simi Pallipurath <simi.pallipurath.com>

Author: simpal01

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

@@ -12648,6 +12648,9 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) {
       {ARM::AEK_CRYPTO,
        {Feature_HasV8Bit},
        {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
+      {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+       {Feature_HasV8_1MMainlineBit},
+       {ARM::HasMVEFloatOps}},
       {ARM::AEK_FP,
        {Feature_HasV8Bit},
        {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}},

llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp

@@ -238,14 +238,18 @@ void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
                         ? ARMBuildAttrs::AllowNeonARMv8_1a
                         : ARMBuildAttrs::AllowNeonARMv8);
   } else {
-    if (STI.hasFeature(ARM::FeatureFPARMv8_D16_SP))
+    if (STI.hasFeature(ARM::FeatureFPARMv8_D16_SP)) {
       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
       // FPU, but there are two different names for it depending on the CPU.
-      emitFPU(STI.hasFeature(ARM::FeatureD32)
-                  ? ARM::FK_FP_ARMV8
-                  : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16
-                                                      : ARM::FK_FPV5_SP_D16));
-    else if (STI.hasFeature(ARM::FeatureVFP4_D16_SP))
+      if (STI.hasFeature(ARM::FeatureD32))
+        emitFPU(ARM::FK_FP_ARMV8);
+      else {
+        emitFPU(STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16
+                                                 : ARM::FK_FPV5_SP_D16);
+        if (STI.hasFeature(ARM::HasMVEFloatOps))
+          emitArchExtension(ARM::AEK_SIMD | ARM::AEK_DSP | ARM::AEK_FP);
+      }
+    } else if (STI.hasFeature(ARM::FeatureVFP4_D16_SP))
       emitFPU(STI.hasFeature(ARM::FeatureD32)
                   ? ARM::FK_VFPV4
                   : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_VFPV4_D16

llvm/test/CodeGen/ARM/arm-v8.1m-check-mve-extension.ll

@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=arm-none-eabi -mcpu=cortex-m85 --float-abi=hard %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-none-eabi -mcpu=cortex-m55 --float-abi=hard %s -o - | FileCheck %s
+
+; CHECK: .fpu   fpv5-d16
+; CHECK-NEXT:  .arch_extension mve.fp
+
+define <4 x float> @vsubf32(<4 x float> %A, <4 x float> %B) {
+; CHECK-LABEL: vsubf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.f32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = fsub <4 x float> %A, %B
+  ret <4 x float> %tmp3
+}

llvm/test/MC/ARM/arm-v8.1m-check-mve-extension.s

@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple thumbv8.1m.main-none-eabi -filetype asm -o - %s 2>&1 | FileCheck %s
+
+.arch_extension mve.fp
+vsub.f32	q0, q0, q1
+// CHECK: vsub.f32	q0, q0, q1
+