reuse MIB and MRI

Author: folkertdev

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -1622,17 +1622,16 @@ bool AArch64LegalizerInfo::legalizeSmallCMGlobalValue(
 
 bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
                                              MachineInstr &MI) const {
-  auto LowerBinOp = [&MI](unsigned Opcode) {
-    MachineIRBuilder MIB(MI);
+  MachineIRBuilder MIB(MI);
+  MachineRegisterInfo &MRI = *MIB.getMRI();
+
+  auto LowerBinOp = [&MI, &MIB](unsigned Opcode) {
     MIB.buildInstr(Opcode, {MI.getOperand(0)},
                    {MI.getOperand(2), MI.getOperand(3)});
     MI.eraseFromParent();
     return true;
   };
 
-  MachineIRBuilder MIB(MI);
-  MachineRegisterInfo &MRI = *MIB.getMRI();
-
   Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
   switch (IntrinsicID) {
   case Intrinsic::vacopy: {
@@ -1788,22 +1787,22 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
     return true;
   }
   case Intrinsic::aarch64_neon_sqadd: {
-    if (MIB.getMRI()->getType(MI.getOperand(0).getReg()).isVector())
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector())
       return LowerBinOp(TargetOpcode::G_SADDSAT);
     break;
   }
   case Intrinsic::aarch64_neon_sqsub: {
-    if (MIB.getMRI()->getType(MI.getOperand(0).getReg()).isVector())
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector())
       return LowerBinOp(TargetOpcode::G_SSUBSAT);
     break;
   }
   case Intrinsic::aarch64_neon_uqadd: {
-    if (MIB.getMRI()->getType(MI.getOperand(0).getReg()).isVector())
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector())
       return LowerBinOp(TargetOpcode::G_UADDSAT);
     break;
   }
   case Intrinsic::aarch64_neon_uqsub: {
-    if (MIB.getMRI()->getType(MI.getOperand(0).getReg()).isVector())
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector())
       return LowerBinOp(TargetOpcode::G_USUBSAT);
     break;
   }