Skip to content

Commit a6eb5ee

Browse files
lenarylenary
authored
[RISCV][NFC] Remove hasStdExtCOrZca (#145139)
As of 20b5728, C always enables Zca, so the check `C || Zca` is equivalent to just checking for `Zca`. This replaces any uses of `HasStdExtCOrZca` with a new `HasStdExtZca` (with the same assembler description, to avoid changes in error messages), and simplifies everywhere where C++ needed to check for either C or Zca. The Subtarget function is just deprecated for the moment.
1 parent f1c1456 commit a6eb5ee

16 files changed

+92
-103
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3296,9 +3296,6 @@ bool isValidInsnFormat(StringRef Format, const MCSubtargetInfo &STI) {
32963296
bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) {
32973297
MCAsmParser &Parser = getParser();
32983298

3299-
bool AllowC = getSTI().hasFeature(RISCV::FeatureStdExtC) ||
3300-
getSTI().hasFeature(RISCV::FeatureStdExtZca);
3301-
33023299
// Expect instruction format as identifier.
33033300
StringRef Format;
33043301
SMLoc ErrorLoc = Parser.getTok().getLoc();
@@ -3342,7 +3339,8 @@ bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) {
33423339
return Error(ErrorLoc, "encoding value does not fit into instruction");
33433340
}
33443341

3345-
if (!AllowC && (EncodingDerivedLength == 2))
3342+
if (!getSTI().hasFeature(RISCV::FeatureStdExtZca) &&
3343+
(EncodingDerivedLength == 2))
33463344
return Error(ErrorLoc, "compressed instructions are not allowed");
33473345

33483346
if (getParser().parseEOL("invalid operand for instruction")) {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -425,11 +425,9 @@ bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
425425
Count -= 1;
426426
}
427427

428-
bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
429-
STI->hasFeature(RISCV::FeatureStdExtZca);
430-
// The canonical nop on RVC is c.nop.
431428
if (Count % 4 == 2) {
432-
OS.write(UseCompressedNop ? "\x01\0" : "\0\0", 2);
429+
// The canonical nop with Zca is c.nop.
430+
OS.write(STI->hasFeature(RISCV::FeatureStdExtZca) ? "\x01\0" : "\0\0", 2);
433431
Count -= 2;
434432
}
435433

@@ -857,9 +855,7 @@ bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
857855
if (!STI->hasFeature(RISCV::FeatureRelax))
858856
return false;
859857

860-
bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
861-
STI->hasFeature(RISCV::FeatureStdExtZca);
862-
unsigned MinNopLen = UseCompressedNop ? 2 : 4;
858+
unsigned MinNopLen = STI->hasFeature(RISCV::FeatureStdExtZca) ? 2 : 4;
863859

864860
if (AF.getAlignment() <= MinNopLen) {
865861
return false;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -280,8 +280,7 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
280280
Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ;
281281

282282
bool UseCompressedBr = false;
283-
if (IsEqTest && (STI.hasFeature(RISCV::FeatureStdExtC) ||
284-
STI.hasFeature(RISCV::FeatureStdExtZca))) {
283+
if (IsEqTest && STI.hasFeature(RISCV::FeatureStdExtZca)) {
285284
if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 &&
286285
SrcReg2.id() == RISCV::X0) {
287286
UseCompressedBr = true;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCObjectFileInfo.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,7 @@ using namespace llvm;
1919

2020
unsigned
2121
RISCVMCObjectFileInfo::getTextSectionAlignment(const MCSubtargetInfo &STI) {
22-
bool RVC = STI.hasFeature(RISCV::FeatureStdExtC) ||
23-
STI.hasFeature(RISCV::FeatureStdExtZca);
24-
return RVC ? 2 : 4;
22+
return STI.hasFeature(RISCV::FeatureStdExtZca) ? 2 : 4;
2523
}
2624

2725
unsigned RISCVMCObjectFileInfo::getTextSectionAlignment() const {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -538,8 +538,7 @@ InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
538538
int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,
539539
bool CompressionCost, bool FreeZeroes) {
540540
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
541-
bool HasRVC = CompressionCost && (STI.hasFeature(RISCV::FeatureStdExtC) ||
542-
STI.hasFeature(RISCV::FeatureStdExtZca));
541+
bool HasRVC = CompressionCost && STI.hasFeature(RISCV::FeatureStdExtZca);
543542
int PlatRegSize = IsRV64 ? 64 : 32;
544543

545544
// Split the constant into platform register sized chunks, and calculate cost

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,7 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
115115
}
116116

117117
void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {
118-
HasRVC = STI.hasFeature(RISCV::FeatureStdExtC) ||
119-
STI.hasFeature(RISCV::FeatureStdExtZca);
118+
HasRVC = STI.hasFeature(RISCV::FeatureStdExtZca);
120119
HasTSO = STI.hasFeature(RISCV::FeatureStdExtZtso);
121120
}
122121

‎llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ class RISCVAsmPrinter : public AsmPrinter {
132132

133133
void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
134134
const MachineInstr &MI) {
135-
unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
135+
unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
136136
unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
137137

138138
auto &Ctx = OutStreamer.getContext();
@@ -165,7 +165,7 @@ void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
165165
// [<def>], <id>, <numBytes>, <target>, <numArgs>
166166
void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
167167
const MachineInstr &MI) {
168-
unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
168+
unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
169169

170170
auto &Ctx = OutStreamer.getContext();
171171
MCSymbol *MILabel = Ctx.createTempSymbol();
@@ -214,7 +214,7 @@ void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
214214

215215
void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
216216
const MachineInstr &MI) {
217-
unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
217+
unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
218218

219219
StatepointOpers SOpers(&MI);
220220
if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
@@ -292,7 +292,7 @@ void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
292292
NontemporalMode += 0b10;
293293

294294
MCInst Hint;
295-
if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs())
295+
if (STI->hasStdExtZca() && STI->enableRVCHintInstrs())
296296
Hint.setOpcode(RISCV::C_ADD_HINT);
297297
else
298298
Hint.setOpcode(RISCV::ADD);
@@ -674,7 +674,7 @@ void RISCVAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
674674
} else {
675675
// Adjust the offset for patchable-function-prefix. This assumes that
676676
// patchable-function-prefix is the same for all functions.
677-
int NopSize = STI->hasStdExtCOrZca() ? 2 : 4;
677+
int NopSize = STI->hasStdExtZca() ? 2 : 4;
678678
int64_t PrefixNops = 0;
679679
(void)MI.getMF()
680680
->getFunction()

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -385,6 +385,13 @@ def FeatureStdExtZca
385385
"part of the C extension, excluding compressed "
386386
"floating point loads/stores">,
387387
RISCVExtensionBitmask<1, 2>;
388+
// FIXME: Update this message - Zca always implies C.
389+
def HasStdExtZca
390+
: Predicate<"Subtarget->hasStdExtZca()">,
391+
AssemblerPredicate<(any_of FeatureStdExtZca),
392+
"'C' (Compressed Instructions) or "
393+
"'Zca' (part of the C extension, excluding "
394+
"compressed floating point loads/stores)">;
388395

389396
def FeatureStdExtC
390397
: RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>,
@@ -393,14 +400,6 @@ def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
393400
AssemblerPredicate<(all_of FeatureStdExtC),
394401
"'C' (Compressed Instructions)">;
395402

396-
397-
def HasStdExtCOrZca
398-
: Predicate<"Subtarget->hasStdExtCOrZca()">,
399-
AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
400-
"'C' (Compressed Instructions) or "
401-
"'Zca' (part of the C extension, excluding "
402-
"compressed floating point loads/stores)">;
403-
404403
def FeatureStdExtZcb
405404
: RISCVExtension<1, 0, "Compressed basic bit manipulation instructions",
406405
[FeatureStdExtZca]>,

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1688,19 +1688,19 @@ static unsigned estimateFunctionSizeInBytes(const MachineFunction &MF,
16881688
//
16891689
// foo
16901690
// bne t5, t6, .rev_cond # `TII->getInstSizeInBytes(MI)` bytes
1691-
// sd s11, 0(sp) # 4 bytes, or 2 bytes in RVC
1691+
// sd s11, 0(sp) # 4 bytes, or 2 bytes with Zca
16921692
// jump .restore, s11 # 8 bytes
16931693
// .rev_cond
16941694
// bar
1695-
// j .dest_bb # 4 bytes, or 2 bytes in RVC
1695+
// j .dest_bb # 4 bytes, or 2 bytes with Zca
16961696
// .restore:
1697-
// ld s11, 0(sp) # 4 bytes, or 2 bytes in RVC
1697+
// ld s11, 0(sp) # 4 bytes, or 2 bytes with Zca
16981698
// .dest:
16991699
// baz
17001700
if (MI.isConditionalBranch())
17011701
FnSize += TII.getInstSizeInBytes(MI);
17021702
if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) {
1703-
if (MF.getSubtarget<RISCVSubtarget>().hasStdExtCOrZca())
1703+
if (MF.getSubtarget<RISCVSubtarget>().hasStdExtZca())
17041704
FnSize += 2 + 8 + 2 + 2;
17051705
else
17061706
FnSize += 4 + 8 + 4 + 4;
@@ -1865,7 +1865,7 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const {
18651865
// instructions be compressed, so try to adjust the amount to the largest
18661866
// offset that stack compression instructions accept when target supports
18671867
// compression instructions.
1868-
if (STI.hasStdExtCOrZca()) {
1868+
if (STI.hasStdExtZca()) {
18691869
// The compression extensions may support the following instructions:
18701870
// riscv32: c.lwsp rd, offset[7:2] => 2^(6 + 2)
18711871
// c.swsp rs2, offset[7:2] => 2^(6 + 2)

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1598,7 +1598,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
15981598
}
15991599

16001600
// Function alignments.
1601-
const Align FunctionAlignment(Subtarget.hasStdExtCOrZca() ? 2 : 4);
1601+
const Align FunctionAlignment(Subtarget.hasStdExtZca() ? 2 : 4);
16021602
setMinFunctionAlignment(FunctionAlignment);
16031603
// Set preferred alignments.
16041604
setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
8888
#include "RISCVGenInstrInfo.inc"
8989

9090
MCInst RISCVInstrInfo::getNop() const {
91-
if (STI.hasStdExtCOrZca())
91+
if (STI.hasStdExtZca())
9292
return MCInstBuilder(RISCV::C_NOP);
9393
return MCInstBuilder(RISCV::ADDI)
9494
.addReg(RISCV::X0)
@@ -1717,7 +1717,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
17171717
if (!MI.memoperands_empty()) {
17181718
MachineMemOperand *MMO = *(MI.memoperands_begin());
17191719
if (STI.hasStdExtZihintntl() && MMO->isNonTemporal()) {
1720-
if (STI.hasStdExtCOrZca() && STI.enableRVCHintInstrs()) {
1720+
if (STI.hasStdExtZca() && STI.enableRVCHintInstrs()) {
17211721
if (isCompressibleInst(MI, STI))
17221722
return 4; // c.ntl.all + c.load/c.store
17231723
return 6; // c.ntl.all + load/store
@@ -1738,7 +1738,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
17381738
case RISCV::PseudoMV_FPR16INX:
17391739
case RISCV::PseudoMV_FPR32INX:
17401740
// MV is always compressible to either c.mv or c.li rd, 0.
1741-
return STI.hasStdExtCOrZca() ? 2 : 4;
1741+
return STI.hasStdExtZca() ? 2 : 4;
17421742
case TargetOpcode::STACKMAP:
17431743
// The upper bound for a stackmap intrinsic is the full length of its shadow
17441744
return StackMapOpers(&MI).getNumPatchBytes();
@@ -1765,7 +1765,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
17651765
return get(Opcode).getSize();
17661766

17671767
// Number of C.NOP or NOP
1768-
return (STI.hasStdExtCOrZca() ? 2 : 4) * Num;
1768+
return (STI.hasStdExtZca() ? 2 : 4) * Num;
17691769
}
17701770
// XRay uses C.JAL + 21 or 33 C.NOP for each sled in RV32 and RV64,
17711771
// respectively.
@@ -3341,14 +3341,14 @@ RISCVInstrInfo::getOutliningCandidateInfo(
33413341
// Each RepeatedSequenceLoc is identical.
33423342
outliner::Candidate &Candidate = RepeatedSequenceLocs[0];
33433343
unsigned InstrSizeCExt =
3344-
Candidate.getMF()->getSubtarget<RISCVSubtarget>().hasStdExtCOrZca() ? 2
3345-
: 4;
3344+
Candidate.getMF()->getSubtarget<RISCVSubtarget>().hasStdExtZca() ? 2 : 4;
33463345
unsigned CallOverhead = 0, FrameOverhead = 0;
33473346

33483347
MachineOutlinerConstructionID MOCI = MachineOutlinerDefault;
33493348
if (Candidate.back().isReturn()) {
33503349
MOCI = MachineOutlinerTailCall;
33513350
// tail call = auipc + jalr in the worst case without linker relaxation.
3351+
// FIXME: This code suggests the JALR can be compressed - how?
33523352
CallOverhead = 4 + InstrSizeCExt;
33533353
// Using tail call we move ret instruction from caller to callee.
33543354
FrameOverhead = 0;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1686,7 +1686,7 @@ defm : BccPat<SETGE, BGE>;
16861686
defm : BccPat<SETULT, BLTU>;
16871687
defm : BccPat<SETUGE, BGEU>;
16881688

1689-
let Predicates = [HasStdExtCOrZca, OptForMinSize] in {
1689+
let Predicates = [HasStdExtZca, OptForMinSize] in {
16901690
def : BrccCompressOpt<SETEQ, BEQ>;
16911691
def : BrccCompressOpt<SETNE, BNE>;
16921692
}

0 commit comments

Comments
 (0)