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[LegalizeTypes][VP] Add split operand support for VP float and integer casting
Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D130685
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5 files changed

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‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2725,6 +2725,8 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
27252725
case ISD::STRICT_UINT_TO_FP:
27262726
case ISD::SINT_TO_FP:
27272727
case ISD::UINT_TO_FP:
2728+
case ISD::VP_SINT_TO_FP:
2729+
case ISD::VP_UINT_TO_FP:
27282730
if (N->getValueType(0).bitsLT(
27292731
N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType()))
27302732
Res = SplitVecOp_TruncateHelper(N);
@@ -2737,6 +2739,8 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
27372739
break;
27382740
case ISD::FP_TO_SINT:
27392741
case ISD::FP_TO_UINT:
2742+
case ISD::VP_FP_TO_SINT:
2743+
case ISD::VP_FP_TO_UINT:
27402744
case ISD::STRICT_FP_TO_SINT:
27412745
case ISD::STRICT_FP_TO_UINT:
27422746
case ISD::STRICT_FP_EXTEND:

‎llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll

Lines changed: 52 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -309,6 +309,50 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
309309
ret <vscale x 2 x i64> %v
310310
}
311311

312+
declare <vscale x 32 x i16> @llvm.vp.fptosi.nxv32i16.nxv32f32(<vscale x 32 x float>, <vscale x 32 x i1>, i32)
313+
314+
define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
315+
; CHECK-LABEL: vfptosi_nxv32i16_nxv32f32:
316+
; CHECK: # %bb.0:
317+
; CHECK-NEXT: addi sp, sp, -16
318+
; CHECK-NEXT: .cfi_def_cfa_offset 16
319+
; CHECK-NEXT: csrr a1, vlenb
320+
; CHECK-NEXT: slli a1, a1, 3
321+
; CHECK-NEXT: sub sp, sp, a1
322+
; CHECK-NEXT: vmv1r.v v24, v0
323+
; CHECK-NEXT: addi a1, sp, 16
324+
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
325+
; CHECK-NEXT: li a2, 0
326+
; CHECK-NEXT: csrr a1, vlenb
327+
; CHECK-NEXT: srli a4, a1, 2
328+
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, mu
329+
; CHECK-NEXT: slli a1, a1, 1
330+
; CHECK-NEXT: sub a3, a0, a1
331+
; CHECK-NEXT: vslidedown.vx v0, v0, a4
332+
; CHECK-NEXT: bltu a0, a3, .LBB25_2
333+
; CHECK-NEXT: # %bb.1:
334+
; CHECK-NEXT: mv a2, a3
335+
; CHECK-NEXT: .LBB25_2:
336+
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
337+
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v16, v0.t
338+
; CHECK-NEXT: bltu a0, a1, .LBB25_4
339+
; CHECK-NEXT: # %bb.3:
340+
; CHECK-NEXT: mv a0, a1
341+
; CHECK-NEXT: .LBB25_4:
342+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
343+
; CHECK-NEXT: vmv1r.v v0, v24
344+
; CHECK-NEXT: addi a0, sp, 16
345+
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
346+
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t
347+
; CHECK-NEXT: csrr a0, vlenb
348+
; CHECK-NEXT: slli a0, a0, 3
349+
; CHECK-NEXT: add sp, sp, a0
350+
; CHECK-NEXT: addi sp, sp, 16
351+
; CHECK-NEXT: ret
352+
%v = call <vscale x 32 x i16> @llvm.vp.fptosi.nxv32i16.nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 %evl)
353+
ret <vscale x 32 x i16> %v
354+
}
355+
312356
declare <vscale x 32 x i32> @llvm.vp.fptosi.nxv32i32.nxv32f32(<vscale x 32 x float>, <vscale x 32 x i1>, i32)
313357

314358
define <vscale x 32 x i32> @vfptosi_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
@@ -322,16 +366,16 @@ define <vscale x 32 x i32> @vfptosi_nxv32i32_nxv32f32(<vscale x 32 x float> %va,
322366
; CHECK-NEXT: slli a1, a1, 1
323367
; CHECK-NEXT: sub a3, a0, a1
324368
; CHECK-NEXT: vslidedown.vx v0, v0, a4
325-
; CHECK-NEXT: bltu a0, a3, .LBB25_2
369+
; CHECK-NEXT: bltu a0, a3, .LBB26_2
326370
; CHECK-NEXT: # %bb.1:
327371
; CHECK-NEXT: mv a2, a3
328-
; CHECK-NEXT: .LBB25_2:
372+
; CHECK-NEXT: .LBB26_2:
329373
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
330374
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16, v0.t
331-
; CHECK-NEXT: bltu a0, a1, .LBB25_4
375+
; CHECK-NEXT: bltu a0, a1, .LBB26_4
332376
; CHECK-NEXT: # %bb.3:
333377
; CHECK-NEXT: mv a0, a1
334-
; CHECK-NEXT: .LBB25_4:
378+
; CHECK-NEXT: .LBB26_4:
335379
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
336380
; CHECK-NEXT: vmv1r.v v0, v24
337381
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
@@ -346,18 +390,18 @@ define <vscale x 32 x i32> @vfptosi_nxv32i32_nxv32f32_unmasked(<vscale x 32 x fl
346390
; CHECK-NEXT: csrr a1, vlenb
347391
; CHECK-NEXT: slli a1, a1, 1
348392
; CHECK-NEXT: mv a2, a0
349-
; CHECK-NEXT: bltu a0, a1, .LBB26_2
393+
; CHECK-NEXT: bltu a0, a1, .LBB27_2
350394
; CHECK-NEXT: # %bb.1:
351395
; CHECK-NEXT: mv a2, a1
352-
; CHECK-NEXT: .LBB26_2:
396+
; CHECK-NEXT: .LBB27_2:
353397
; CHECK-NEXT: li a3, 0
354398
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
355399
; CHECK-NEXT: sub a1, a0, a1
356400
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
357-
; CHECK-NEXT: bltu a0, a1, .LBB26_4
401+
; CHECK-NEXT: bltu a0, a1, .LBB27_4
358402
; CHECK-NEXT: # %bb.3:
359403
; CHECK-NEXT: mv a3, a1
360-
; CHECK-NEXT: .LBB26_4:
404+
; CHECK-NEXT: .LBB27_4:
361405
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
362406
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16
363407
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll

Lines changed: 52 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -309,6 +309,50 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
309309
ret <vscale x 2 x i64> %v
310310
}
311311

312+
declare <vscale x 32 x i16> @llvm.vp.fptoui.nxv32i16.nxv32f32(<vscale x 32 x float>, <vscale x 32 x i1>, i32)
313+
314+
define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
315+
; CHECK-LABEL: vfptoui_nxv32i16_nxv32f32:
316+
; CHECK: # %bb.0:
317+
; CHECK-NEXT: addi sp, sp, -16
318+
; CHECK-NEXT: .cfi_def_cfa_offset 16
319+
; CHECK-NEXT: csrr a1, vlenb
320+
; CHECK-NEXT: slli a1, a1, 3
321+
; CHECK-NEXT: sub sp, sp, a1
322+
; CHECK-NEXT: vmv1r.v v24, v0
323+
; CHECK-NEXT: addi a1, sp, 16
324+
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
325+
; CHECK-NEXT: li a2, 0
326+
; CHECK-NEXT: csrr a1, vlenb
327+
; CHECK-NEXT: srli a4, a1, 2
328+
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, mu
329+
; CHECK-NEXT: slli a1, a1, 1
330+
; CHECK-NEXT: sub a3, a0, a1
331+
; CHECK-NEXT: vslidedown.vx v0, v0, a4
332+
; CHECK-NEXT: bltu a0, a3, .LBB25_2
333+
; CHECK-NEXT: # %bb.1:
334+
; CHECK-NEXT: mv a2, a3
335+
; CHECK-NEXT: .LBB25_2:
336+
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
337+
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v16, v0.t
338+
; CHECK-NEXT: bltu a0, a1, .LBB25_4
339+
; CHECK-NEXT: # %bb.3:
340+
; CHECK-NEXT: mv a0, a1
341+
; CHECK-NEXT: .LBB25_4:
342+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
343+
; CHECK-NEXT: vmv1r.v v0, v24
344+
; CHECK-NEXT: addi a0, sp, 16
345+
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
346+
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t
347+
; CHECK-NEXT: csrr a0, vlenb
348+
; CHECK-NEXT: slli a0, a0, 3
349+
; CHECK-NEXT: add sp, sp, a0
350+
; CHECK-NEXT: addi sp, sp, 16
351+
; CHECK-NEXT: ret
352+
%v = call <vscale x 32 x i16> @llvm.vp.fptoui.nxv32i16.nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 %evl)
353+
ret <vscale x 32 x i16> %v
354+
}
355+
312356
declare <vscale x 32 x i32> @llvm.vp.fptoui.nxv32i32.nxv32f32(<vscale x 32 x float>, <vscale x 32 x i1>, i32)
313357

314358
define <vscale x 32 x i32> @vfptoui_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
@@ -322,16 +366,16 @@ define <vscale x 32 x i32> @vfptoui_nxv32i32_nxv32f32(<vscale x 32 x float> %va,
322366
; CHECK-NEXT: slli a1, a1, 1
323367
; CHECK-NEXT: sub a3, a0, a1
324368
; CHECK-NEXT: vslidedown.vx v0, v0, a4
325-
; CHECK-NEXT: bltu a0, a3, .LBB25_2
369+
; CHECK-NEXT: bltu a0, a3, .LBB26_2
326370
; CHECK-NEXT: # %bb.1:
327371
; CHECK-NEXT: mv a2, a3
328-
; CHECK-NEXT: .LBB25_2:
372+
; CHECK-NEXT: .LBB26_2:
329373
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
330374
; CHECK-NEXT: vfcvt.rtz.xu.f.v v16, v16, v0.t
331-
; CHECK-NEXT: bltu a0, a1, .LBB25_4
375+
; CHECK-NEXT: bltu a0, a1, .LBB26_4
332376
; CHECK-NEXT: # %bb.3:
333377
; CHECK-NEXT: mv a0, a1
334-
; CHECK-NEXT: .LBB25_4:
378+
; CHECK-NEXT: .LBB26_4:
335379
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
336380
; CHECK-NEXT: vmv1r.v v0, v24
337381
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8, v0.t
@@ -346,18 +390,18 @@ define <vscale x 32 x i32> @vfptoui_nxv32i32_nxv32f32_unmasked(<vscale x 32 x fl
346390
; CHECK-NEXT: csrr a1, vlenb
347391
; CHECK-NEXT: slli a1, a1, 1
348392
; CHECK-NEXT: mv a2, a0
349-
; CHECK-NEXT: bltu a0, a1, .LBB26_2
393+
; CHECK-NEXT: bltu a0, a1, .LBB27_2
350394
; CHECK-NEXT: # %bb.1:
351395
; CHECK-NEXT: mv a2, a1
352-
; CHECK-NEXT: .LBB26_2:
396+
; CHECK-NEXT: .LBB27_2:
353397
; CHECK-NEXT: li a3, 0
354398
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
355399
; CHECK-NEXT: sub a1, a0, a1
356400
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
357-
; CHECK-NEXT: bltu a0, a1, .LBB26_4
401+
; CHECK-NEXT: bltu a0, a1, .LBB27_4
358402
; CHECK-NEXT: # %bb.3:
359403
; CHECK-NEXT: mv a3, a1
360-
; CHECK-NEXT: .LBB26_4:
404+
; CHECK-NEXT: .LBB27_4:
361405
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
362406
; CHECK-NEXT: vfcvt.rtz.xu.f.v v16, v16
363407
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll

Lines changed: 52 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -301,6 +301,50 @@ define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
301301
ret <vscale x 2 x double> %v
302302
}
303303

304+
declare <vscale x 32 x half> @llvm.vp.sitofp.nxv32f16.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i1>, i32)
305+
306+
define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
307+
; CHECK-LABEL: vsitofp_nxv32f16_nxv32i32:
308+
; CHECK: # %bb.0:
309+
; CHECK-NEXT: addi sp, sp, -16
310+
; CHECK-NEXT: .cfi_def_cfa_offset 16
311+
; CHECK-NEXT: csrr a1, vlenb
312+
; CHECK-NEXT: slli a1, a1, 3
313+
; CHECK-NEXT: sub sp, sp, a1
314+
; CHECK-NEXT: vmv1r.v v24, v0
315+
; CHECK-NEXT: addi a1, sp, 16
316+
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
317+
; CHECK-NEXT: li a2, 0
318+
; CHECK-NEXT: csrr a1, vlenb
319+
; CHECK-NEXT: srli a4, a1, 2
320+
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, mu
321+
; CHECK-NEXT: slli a1, a1, 1
322+
; CHECK-NEXT: sub a3, a0, a1
323+
; CHECK-NEXT: vslidedown.vx v0, v0, a4
324+
; CHECK-NEXT: bltu a0, a3, .LBB25_2
325+
; CHECK-NEXT: # %bb.1:
326+
; CHECK-NEXT: mv a2, a3
327+
; CHECK-NEXT: .LBB25_2:
328+
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
329+
; CHECK-NEXT: vfncvt.f.x.w v12, v16, v0.t
330+
; CHECK-NEXT: bltu a0, a1, .LBB25_4
331+
; CHECK-NEXT: # %bb.3:
332+
; CHECK-NEXT: mv a0, a1
333+
; CHECK-NEXT: .LBB25_4:
334+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
335+
; CHECK-NEXT: vmv1r.v v0, v24
336+
; CHECK-NEXT: addi a0, sp, 16
337+
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
338+
; CHECK-NEXT: vfncvt.f.x.w v8, v16, v0.t
339+
; CHECK-NEXT: csrr a0, vlenb
340+
; CHECK-NEXT: slli a0, a0, 3
341+
; CHECK-NEXT: add sp, sp, a0
342+
; CHECK-NEXT: addi sp, sp, 16
343+
; CHECK-NEXT: ret
344+
%v = call <vscale x 32 x half> @llvm.vp.sitofp.nxv32f16.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 %evl)
345+
ret <vscale x 32 x half> %v
346+
}
347+
304348
declare <vscale x 32 x float> @llvm.vp.sitofp.nxv32f32.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i1>, i32)
305349

306350
define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
@@ -314,16 +358,16 @@ define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va,
314358
; CHECK-NEXT: slli a1, a1, 1
315359
; CHECK-NEXT: sub a3, a0, a1
316360
; CHECK-NEXT: vslidedown.vx v0, v0, a4
317-
; CHECK-NEXT: bltu a0, a3, .LBB25_2
361+
; CHECK-NEXT: bltu a0, a3, .LBB26_2
318362
; CHECK-NEXT: # %bb.1:
319363
; CHECK-NEXT: mv a2, a3
320-
; CHECK-NEXT: .LBB25_2:
364+
; CHECK-NEXT: .LBB26_2:
321365
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
322366
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
323-
; CHECK-NEXT: bltu a0, a1, .LBB25_4
367+
; CHECK-NEXT: bltu a0, a1, .LBB26_4
324368
; CHECK-NEXT: # %bb.3:
325369
; CHECK-NEXT: mv a0, a1
326-
; CHECK-NEXT: .LBB25_4:
370+
; CHECK-NEXT: .LBB26_4:
327371
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
328372
; CHECK-NEXT: vmv1r.v v0, v24
329373
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -338,18 +382,18 @@ define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32_unmasked(<vscale x 32 x
338382
; CHECK-NEXT: csrr a1, vlenb
339383
; CHECK-NEXT: slli a1, a1, 1
340384
; CHECK-NEXT: mv a2, a0
341-
; CHECK-NEXT: bltu a0, a1, .LBB26_2
385+
; CHECK-NEXT: bltu a0, a1, .LBB27_2
342386
; CHECK-NEXT: # %bb.1:
343387
; CHECK-NEXT: mv a2, a1
344-
; CHECK-NEXT: .LBB26_2:
388+
; CHECK-NEXT: .LBB27_2:
345389
; CHECK-NEXT: li a3, 0
346390
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
347391
; CHECK-NEXT: sub a1, a0, a1
348392
; CHECK-NEXT: vfcvt.f.x.v v8, v8
349-
; CHECK-NEXT: bltu a0, a1, .LBB26_4
393+
; CHECK-NEXT: bltu a0, a1, .LBB27_4
350394
; CHECK-NEXT: # %bb.3:
351395
; CHECK-NEXT: mv a3, a1
352-
; CHECK-NEXT: .LBB26_4:
396+
; CHECK-NEXT: .LBB27_4:
353397
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
354398
; CHECK-NEXT: vfcvt.f.x.v v16, v16
355399
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll

Lines changed: 52 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -301,6 +301,50 @@ define <vscale x 2 x double> @vuitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
301301
ret <vscale x 2 x double> %v
302302
}
303303

304+
declare <vscale x 32 x half> @llvm.vp.uitofp.nxv32f16.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i1>, i32)
305+
306+
define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
307+
; CHECK-LABEL: vuitofp_nxv32f16_nxv32i32:
308+
; CHECK: # %bb.0:
309+
; CHECK-NEXT: addi sp, sp, -16
310+
; CHECK-NEXT: .cfi_def_cfa_offset 16
311+
; CHECK-NEXT: csrr a1, vlenb
312+
; CHECK-NEXT: slli a1, a1, 3
313+
; CHECK-NEXT: sub sp, sp, a1
314+
; CHECK-NEXT: vmv1r.v v24, v0
315+
; CHECK-NEXT: addi a1, sp, 16
316+
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
317+
; CHECK-NEXT: li a2, 0
318+
; CHECK-NEXT: csrr a1, vlenb
319+
; CHECK-NEXT: srli a4, a1, 2
320+
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, mu
321+
; CHECK-NEXT: slli a1, a1, 1
322+
; CHECK-NEXT: sub a3, a0, a1
323+
; CHECK-NEXT: vslidedown.vx v0, v0, a4
324+
; CHECK-NEXT: bltu a0, a3, .LBB25_2
325+
; CHECK-NEXT: # %bb.1:
326+
; CHECK-NEXT: mv a2, a3
327+
; CHECK-NEXT: .LBB25_2:
328+
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
329+
; CHECK-NEXT: vfncvt.f.xu.w v12, v16, v0.t
330+
; CHECK-NEXT: bltu a0, a1, .LBB25_4
331+
; CHECK-NEXT: # %bb.3:
332+
; CHECK-NEXT: mv a0, a1
333+
; CHECK-NEXT: .LBB25_4:
334+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
335+
; CHECK-NEXT: vmv1r.v v0, v24
336+
; CHECK-NEXT: addi a0, sp, 16
337+
; CHECK-NEXT: vl8re8.v v16, (a0) # Unknown-size Folded Reload
338+
; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t
339+
; CHECK-NEXT: csrr a0, vlenb
340+
; CHECK-NEXT: slli a0, a0, 3
341+
; CHECK-NEXT: add sp, sp, a0
342+
; CHECK-NEXT: addi sp, sp, 16
343+
; CHECK-NEXT: ret
344+
%v = call <vscale x 32 x half> @llvm.vp.uitofp.nxv32f16.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 %evl)
345+
ret <vscale x 32 x half> %v
346+
}
347+
304348
declare <vscale x 32 x float> @llvm.vp.uitofp.nxv32f32.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i1>, i32)
305349

306350
define <vscale x 32 x float> @vuitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
@@ -314,16 +358,16 @@ define <vscale x 32 x float> @vuitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va,
314358
; CHECK-NEXT: slli a1, a1, 1
315359
; CHECK-NEXT: sub a3, a0, a1
316360
; CHECK-NEXT: vslidedown.vx v0, v0, a4
317-
; CHECK-NEXT: bltu a0, a3, .LBB25_2
361+
; CHECK-NEXT: bltu a0, a3, .LBB26_2
318362
; CHECK-NEXT: # %bb.1:
319363
; CHECK-NEXT: mv a2, a3
320-
; CHECK-NEXT: .LBB25_2:
364+
; CHECK-NEXT: .LBB26_2:
321365
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
322366
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
323-
; CHECK-NEXT: bltu a0, a1, .LBB25_4
367+
; CHECK-NEXT: bltu a0, a1, .LBB26_4
324368
; CHECK-NEXT: # %bb.3:
325369
; CHECK-NEXT: mv a0, a1
326-
; CHECK-NEXT: .LBB25_4:
370+
; CHECK-NEXT: .LBB26_4:
327371
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
328372
; CHECK-NEXT: vmv1r.v v0, v24
329373
; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
@@ -338,18 +382,18 @@ define <vscale x 32 x float> @vuitofp_nxv32f32_nxv32i32_unmasked(<vscale x 32 x
338382
; CHECK-NEXT: csrr a1, vlenb
339383
; CHECK-NEXT: slli a1, a1, 1
340384
; CHECK-NEXT: mv a2, a0
341-
; CHECK-NEXT: bltu a0, a1, .LBB26_2
385+
; CHECK-NEXT: bltu a0, a1, .LBB27_2
342386
; CHECK-NEXT: # %bb.1:
343387
; CHECK-NEXT: mv a2, a1
344-
; CHECK-NEXT: .LBB26_2:
388+
; CHECK-NEXT: .LBB27_2:
345389
; CHECK-NEXT: li a3, 0
346390
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
347391
; CHECK-NEXT: sub a1, a0, a1
348392
; CHECK-NEXT: vfcvt.f.xu.v v8, v8
349-
; CHECK-NEXT: bltu a0, a1, .LBB26_4
393+
; CHECK-NEXT: bltu a0, a1, .LBB27_4
350394
; CHECK-NEXT: # %bb.3:
351395
; CHECK-NEXT: mv a3, a1
352-
; CHECK-NEXT: .LBB26_4:
396+
; CHECK-NEXT: .LBB27_4:
353397
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, mu
354398
; CHECK-NEXT: vfcvt.f.xu.v v16, v16
355399
; CHECK-NEXT: ret

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