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Revert "[RISCV] Fix wrong CFI directives"
test/DebugInfo/RISCV/relax-debug-frame.ll wasn't properly updated.
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‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -233,13 +233,16 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
233233
}
234234
}
235235

236+
// FIXME Fix emission of .cfi_restore and .cfi_def_cfa CFI directives that can
237+
// incorrectly affect subsequent basic blocks.
236238
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
237239
MachineBasicBlock &MBB) const {
238240
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
239241
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
240242
MachineFrameInfo &MFI = MF.getFrameInfo();
241243
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
242244
DebugLoc DL = MBBI->getDebugLoc();
245+
const RISCVInstrInfo *TII = STI.getInstrInfo();
243246
Register FPReg = getFPReg(STI);
244247
Register SPReg = getSPReg(STI);
245248

@@ -268,13 +271,65 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
268271

269272
adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
270273
MachineInstr::FrameDestroy);
274+
275+
// Emit ".cfi_def_cfa_offset FirstSPAdjustAmount" if using an sp-based CFA
276+
if (!hasFP(MF)) {
277+
unsigned CFIIndex = MF.addFrameInst(
278+
MCCFIInstruction::createDefCfaOffset(nullptr, -FirstSPAdjustAmount));
279+
BuildMI(MBB, LastFrameDestroy, DL,
280+
TII->get(TargetOpcode::CFI_INSTRUCTION))
281+
.addCFIIndex(CFIIndex);
282+
}
283+
}
284+
285+
if (hasFP(MF)) {
286+
// To find the instruction restoring FP from stack.
287+
for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
288+
if (I->mayLoad() && I->getOperand(0).isReg()) {
289+
Register DestReg = I->getOperand(0).getReg();
290+
if (DestReg == FPReg) {
291+
// If there is frame pointer, after restoring $fp registers, we
292+
// need adjust CFA back to the correct sp-based offset.
293+
// Emit ".cfi_def_cfa $sp, CFAOffset"
294+
uint64_t CFAOffset =
295+
FirstSPAdjustAmount
296+
? -FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
297+
: -FPOffset;
298+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
299+
nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
300+
BuildMI(MBB, std::next(I), DL,
301+
TII->get(TargetOpcode::CFI_INSTRUCTION))
302+
.addCFIIndex(CFIIndex);
303+
break;
304+
}
305+
}
306+
}
307+
}
308+
309+
// Add CFI directives for callee-saved registers.
310+
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
311+
// Iterate over list of callee-saved registers and emit .cfi_restore
312+
// directives.
313+
for (const auto &Entry : CSI) {
314+
Register Reg = Entry.getReg();
315+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
316+
nullptr, RI->getDwarfRegNum(Reg, true)));
317+
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
318+
.addCFIIndex(CFIIndex);
271319
}
272320

273321
if (FirstSPAdjustAmount)
274322
StackSize = FirstSPAdjustAmount;
275323

276324
// Deallocate stack
277325
adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
326+
327+
// After restoring $sp, we need to adjust CFA to $(sp + 0)
328+
// Emit ".cfi_def_cfa_offset 0"
329+
unsigned CFIIndex =
330+
MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
331+
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
332+
.addCFIIndex(CFIIndex);
278333
}
279334

280335
int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,

‎llvm/test/CodeGen/RISCV/exception-pointer-register.ll

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,11 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
4040
; RV32I-NEXT: lw s1, 4(sp)
4141
; RV32I-NEXT: lw s0, 8(sp)
4242
; RV32I-NEXT: lw ra, 12(sp)
43+
; RV32I-NEXT: .cfi_restore ra
44+
; RV32I-NEXT: .cfi_restore s0
45+
; RV32I-NEXT: .cfi_restore s1
4346
; RV32I-NEXT: addi sp, sp, 16
47+
; RV32I-NEXT: .cfi_def_cfa_offset 0
4448
; RV32I-NEXT: ret
4549
; RV32I-NEXT: .LBB0_4: # %lpad
4650
; RV32I-NEXT: .Ltmp4:
@@ -77,7 +81,11 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
7781
; RV64I-NEXT: ld s1, 8(sp)
7882
; RV64I-NEXT: ld s0, 16(sp)
7983
; RV64I-NEXT: ld ra, 24(sp)
84+
; RV64I-NEXT: .cfi_restore ra
85+
; RV64I-NEXT: .cfi_restore s0
86+
; RV64I-NEXT: .cfi_restore s1
8087
; RV64I-NEXT: addi sp, sp, 32
88+
; RV64I-NEXT: .cfi_def_cfa_offset 0
8189
; RV64I-NEXT: ret
8290
; RV64I-NEXT: .LBB0_4: # %lpad
8391
; RV64I-NEXT: .Ltmp4:
@@ -111,10 +119,12 @@ end2:
111119
define internal void @callee(i1* %p) {
112120
; RV32I-LABEL: callee:
113121
; RV32I: # %bb.0:
122+
; RV32I-NEXT: .cfi_def_cfa_offset 0
114123
; RV32I-NEXT: ret
115124
;
116125
; RV64I-LABEL: callee:
117126
; RV64I: # %bb.0:
127+
; RV64I-NEXT: .cfi_def_cfa_offset 0
118128
; RV64I-NEXT: ret
119129
ret void
120130
}

‎llvm/test/CodeGen/RISCV/frame-info.ll

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,12 @@
99
define void @trivial() {
1010
; RV32-LABEL: trivial:
1111
; RV32: # %bb.0:
12+
; RV32-NEXT: .cfi_def_cfa_offset 0
1213
; RV32-NEXT: ret
1314
;
1415
; RV64-LABEL: trivial:
1516
; RV64: # %bb.0:
17+
; RV64-NEXT: .cfi_def_cfa_offset 0
1618
; RV64-NEXT: ret
1719
;
1820
; RV32-WITHFP-LABEL: trivial:
@@ -26,8 +28,12 @@ define void @trivial() {
2628
; RV32-WITHFP-NEXT: addi s0, sp, 16
2729
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
2830
; RV32-WITHFP-NEXT: lw s0, 8(sp)
31+
; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
2932
; RV32-WITHFP-NEXT: lw ra, 12(sp)
33+
; RV32-WITHFP-NEXT: .cfi_restore ra
34+
; RV32-WITHFP-NEXT: .cfi_restore s0
3035
; RV32-WITHFP-NEXT: addi sp, sp, 16
36+
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
3137
; RV32-WITHFP-NEXT: ret
3238
;
3339
; RV64-WITHFP-LABEL: trivial:
@@ -41,8 +47,12 @@ define void @trivial() {
4147
; RV64-WITHFP-NEXT: addi s0, sp, 16
4248
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
4349
; RV64-WITHFP-NEXT: ld s0, 0(sp)
50+
; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
4451
; RV64-WITHFP-NEXT: ld ra, 8(sp)
52+
; RV64-WITHFP-NEXT: .cfi_restore ra
53+
; RV64-WITHFP-NEXT: .cfi_restore s0
4554
; RV64-WITHFP-NEXT: addi sp, sp, 16
55+
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
4656
; RV64-WITHFP-NEXT: ret
4757
ret void
4858
}
@@ -65,8 +75,12 @@ define void @stack_alloc(i32 signext %size) {
6575
; RV32-NEXT: call callee_with_args
6676
; RV32-NEXT: addi sp, s0, -16
6777
; RV32-NEXT: lw s0, 8(sp)
78+
; RV32-NEXT: .cfi_def_cfa sp, 16
6879
; RV32-NEXT: lw ra, 12(sp)
80+
; RV32-NEXT: .cfi_restore ra
81+
; RV32-NEXT: .cfi_restore s0
6982
; RV32-NEXT: addi sp, sp, 16
83+
; RV32-NEXT: .cfi_def_cfa_offset 0
7084
; RV32-NEXT: ret
7185
;
7286
; RV64-LABEL: stack_alloc:
@@ -91,8 +105,12 @@ define void @stack_alloc(i32 signext %size) {
91105
; RV64-NEXT: call callee_with_args
92106
; RV64-NEXT: addi sp, s0, -16
93107
; RV64-NEXT: ld s0, 0(sp)
108+
; RV64-NEXT: .cfi_def_cfa sp, 16
94109
; RV64-NEXT: ld ra, 8(sp)
110+
; RV64-NEXT: .cfi_restore ra
111+
; RV64-NEXT: .cfi_restore s0
95112
; RV64-NEXT: addi sp, sp, 16
113+
; RV64-NEXT: .cfi_def_cfa_offset 0
96114
; RV64-NEXT: ret
97115
;
98116
; RV32-WITHFP-LABEL: stack_alloc:
@@ -112,8 +130,12 @@ define void @stack_alloc(i32 signext %size) {
112130
; RV32-WITHFP-NEXT: call callee_with_args
113131
; RV32-WITHFP-NEXT: addi sp, s0, -16
114132
; RV32-WITHFP-NEXT: lw s0, 8(sp)
133+
; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
115134
; RV32-WITHFP-NEXT: lw ra, 12(sp)
135+
; RV32-WITHFP-NEXT: .cfi_restore ra
136+
; RV32-WITHFP-NEXT: .cfi_restore s0
116137
; RV32-WITHFP-NEXT: addi sp, sp, 16
138+
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
117139
; RV32-WITHFP-NEXT: ret
118140
;
119141
; RV64-WITHFP-LABEL: stack_alloc:
@@ -138,15 +160,21 @@ define void @stack_alloc(i32 signext %size) {
138160
; RV64-WITHFP-NEXT: call callee_with_args
139161
; RV64-WITHFP-NEXT: addi sp, s0, -16
140162
; RV64-WITHFP-NEXT: ld s0, 0(sp)
163+
; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
141164
; RV64-WITHFP-NEXT: ld ra, 8(sp)
165+
; RV64-WITHFP-NEXT: .cfi_restore ra
166+
; RV64-WITHFP-NEXT: .cfi_restore s0
142167
; RV64-WITHFP-NEXT: addi sp, sp, 16
168+
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
143169
; RV64-WITHFP-NEXT: ret
144170
entry:
145171
%0 = alloca i8, i32 %size, align 16
146172
call void @callee_with_args(i8* nonnull %0) #2
147173
ret void
148174
}
149175

176+
; FIXME: fix use of .cfi_restore with wrong CFAs
177+
150178
define void @branch_and_tail_call(i1 %a) {
151179
; RV32-LABEL: branch_and_tail_call:
152180
; RV32: # %bb.0:
@@ -158,12 +186,16 @@ define void @branch_and_tail_call(i1 %a) {
158186
; RV32-NEXT: beqz a0, .LBB2_2
159187
; RV32-NEXT: # %bb.1: # %blue_pill
160188
; RV32-NEXT: lw ra, 12(sp)
189+
; RV32-NEXT: .cfi_restore ra
161190
; RV32-NEXT: addi sp, sp, 16
191+
; RV32-NEXT: .cfi_def_cfa_offset 0
162192
; RV32-NEXT: tail callee1
163193
; RV32-NEXT: .LBB2_2: # %red_pill
164194
; RV32-NEXT: call callee2
165195
; RV32-NEXT: lw ra, 12(sp)
196+
; RV32-NEXT: .cfi_restore ra
166197
; RV32-NEXT: addi sp, sp, 16
198+
; RV32-NEXT: .cfi_def_cfa_offset 0
167199
; RV32-NEXT: ret
168200
;
169201
; RV64-LABEL: branch_and_tail_call:
@@ -176,12 +208,16 @@ define void @branch_and_tail_call(i1 %a) {
176208
; RV64-NEXT: beqz a0, .LBB2_2
177209
; RV64-NEXT: # %bb.1: # %blue_pill
178210
; RV64-NEXT: ld ra, 8(sp)
211+
; RV64-NEXT: .cfi_restore ra
179212
; RV64-NEXT: addi sp, sp, 16
213+
; RV64-NEXT: .cfi_def_cfa_offset 0
180214
; RV64-NEXT: tail callee1
181215
; RV64-NEXT: .LBB2_2: # %red_pill
182216
; RV64-NEXT: call callee2
183217
; RV64-NEXT: ld ra, 8(sp)
218+
; RV64-NEXT: .cfi_restore ra
184219
; RV64-NEXT: addi sp, sp, 16
220+
; RV64-NEXT: .cfi_def_cfa_offset 0
185221
; RV64-NEXT: ret
186222
;
187223
; RV32-WITHFP-LABEL: branch_and_tail_call:
@@ -198,14 +234,22 @@ define void @branch_and_tail_call(i1 %a) {
198234
; RV32-WITHFP-NEXT: beqz a0, .LBB2_2
199235
; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill
200236
; RV32-WITHFP-NEXT: lw s0, 8(sp)
237+
; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
201238
; RV32-WITHFP-NEXT: lw ra, 12(sp)
239+
; RV32-WITHFP-NEXT: .cfi_restore ra
240+
; RV32-WITHFP-NEXT: .cfi_restore s0
202241
; RV32-WITHFP-NEXT: addi sp, sp, 16
242+
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
203243
; RV32-WITHFP-NEXT: tail callee1
204244
; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill
205245
; RV32-WITHFP-NEXT: call callee2
206246
; RV32-WITHFP-NEXT: lw s0, 8(sp)
247+
; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
207248
; RV32-WITHFP-NEXT: lw ra, 12(sp)
249+
; RV32-WITHFP-NEXT: .cfi_restore ra
250+
; RV32-WITHFP-NEXT: .cfi_restore s0
208251
; RV32-WITHFP-NEXT: addi sp, sp, 16
252+
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
209253
; RV32-WITHFP-NEXT: ret
210254
;
211255
; RV64-WITHFP-LABEL: branch_and_tail_call:
@@ -222,14 +266,22 @@ define void @branch_and_tail_call(i1 %a) {
222266
; RV64-WITHFP-NEXT: beqz a0, .LBB2_2
223267
; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill
224268
; RV64-WITHFP-NEXT: ld s0, 0(sp)
269+
; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
225270
; RV64-WITHFP-NEXT: ld ra, 8(sp)
271+
; RV64-WITHFP-NEXT: .cfi_restore ra
272+
; RV64-WITHFP-NEXT: .cfi_restore s0
226273
; RV64-WITHFP-NEXT: addi sp, sp, 16
274+
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
227275
; RV64-WITHFP-NEXT: tail callee1
228276
; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill
229277
; RV64-WITHFP-NEXT: call callee2
230278
; RV64-WITHFP-NEXT: ld s0, 0(sp)
279+
; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
231280
; RV64-WITHFP-NEXT: ld ra, 8(sp)
281+
; RV64-WITHFP-NEXT: .cfi_restore ra
282+
; RV64-WITHFP-NEXT: .cfi_restore s0
232283
; RV64-WITHFP-NEXT: addi sp, sp, 16
284+
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
233285
; RV64-WITHFP-NEXT: ret
234286
br i1 %a, label %blue_pill, label %red_pill
235287
blue_pill:

‎llvm/test/CodeGen/RISCV/large-stack.ll

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ define void @test() {
1616
; RV32I-FPELIM-NEXT: lui a0, 74565
1717
; RV32I-FPELIM-NEXT: addi a0, a0, 1664
1818
; RV32I-FPELIM-NEXT: add sp, sp, a0
19+
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
1920
; RV32I-FPELIM-NEXT: ret
2021
;
2122
; RV32I-WITHFP-LABEL: test:
@@ -35,8 +36,12 @@ define void @test() {
3536
; RV32I-WITHFP-NEXT: addi a0, a0, -352
3637
; RV32I-WITHFP-NEXT: add sp, sp, a0
3738
; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
39+
; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 2032
3840
; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
41+
; RV32I-WITHFP-NEXT: .cfi_restore ra
42+
; RV32I-WITHFP-NEXT: .cfi_restore s0
3943
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
44+
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
4045
; RV32I-WITHFP-NEXT: ret
4146
%tmp = alloca [ 305419896 x i8 ] , align 4
4247
ret void
@@ -72,9 +77,13 @@ define void @test_emergency_spill_slot(i32 %a) {
7277
; RV32I-FPELIM-NEXT: lui a0, 97
7378
; RV32I-FPELIM-NEXT: addi a0, a0, 672
7479
; RV32I-FPELIM-NEXT: add sp, sp, a0
80+
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
7581
; RV32I-FPELIM-NEXT: lw s1, 2024(sp)
7682
; RV32I-FPELIM-NEXT: lw s0, 2028(sp)
83+
; RV32I-FPELIM-NEXT: .cfi_restore s0
84+
; RV32I-FPELIM-NEXT: .cfi_restore s1
7785
; RV32I-FPELIM-NEXT: addi sp, sp, 2032
86+
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
7887
; RV32I-FPELIM-NEXT: ret
7988
;
8089
; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
@@ -114,8 +123,14 @@ define void @test_emergency_spill_slot(i32 %a) {
114123
; RV32I-WITHFP-NEXT: lw s2, 2016(sp)
115124
; RV32I-WITHFP-NEXT: lw s1, 2020(sp)
116125
; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
126+
; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 2032
117127
; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
128+
; RV32I-WITHFP-NEXT: .cfi_restore ra
129+
; RV32I-WITHFP-NEXT: .cfi_restore s0
130+
; RV32I-WITHFP-NEXT: .cfi_restore s1
131+
; RV32I-WITHFP-NEXT: .cfi_restore s2
118132
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
133+
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
119134
; RV32I-WITHFP-NEXT: ret
120135
%data = alloca [ 100000 x i32 ] , align 4
121136
%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000

‎llvm/test/CodeGen/RISCV/split-offsets.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
2222
; RV32I-NEXT: sw a3, 4(a0)
2323
; RV32I-NEXT: sw a3, 0(a1)
2424
; RV32I-NEXT: sw a2, 4(a1)
25+
; RV32I-NEXT: .cfi_def_cfa_offset 0
2526
; RV32I-NEXT: ret
2627
;
2728
; RV64I-LABEL: test1:
@@ -37,6 +38,7 @@ define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
3738
; RV64I-NEXT: sw a3, 4(a0)
3839
; RV64I-NEXT: sw a3, 0(a1)
3940
; RV64I-NEXT: sw a2, 4(a1)
41+
; RV64I-NEXT: .cfi_def_cfa_offset 0
4042
; RV64I-NEXT: ret
4143
entry:
4244
%s = load [65536 x i32]*, [65536 x i32]** %sp
@@ -72,6 +74,7 @@ define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
7274
; RV32I-NEXT: mv a3, a4
7375
; RV32I-NEXT: blt a3, a2, .LBB1_1
7476
; RV32I-NEXT: .LBB1_2: # %while_end
77+
; RV32I-NEXT: .cfi_def_cfa_offset 0
7578
; RV32I-NEXT: ret
7679
;
7780
; RV64I-LABEL: test2:
@@ -96,6 +99,7 @@ define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
9699
; RV64I-NEXT: sext.w a4, a3
97100
; RV64I-NEXT: blt a4, a2, .LBB1_1
98101
; RV64I-NEXT: .LBB1_2: # %while_end
102+
; RV64I-NEXT: .cfi_def_cfa_offset 0
99103
; RV64I-NEXT: ret
100104
entry:
101105
%s = load [65536 x i32]*, [65536 x i32]** %sp

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