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[Clang][SVE2.1] Add floating-point variants of svrevd_XX (#75117)
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‎clang/include/clang/Basic/arm_sve.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2077,11 +2077,11 @@ def SVBFMLSLB_LANE : SInst<"svbfmlslb_lane[_{d}]", "dd$$i", "f", MergeNone, "aar
20772077
def SVBFMLSLT_LANE : SInst<"svbfmlslt_lane[_{d}]", "dd$$i", "f", MergeNone, "aarch64_sve_bfmlslt_lane", [IsOverloadNone], [ImmCheck<3, ImmCheck0_7>]>;
20782078
}
20792079

2080-
let TargetGuard = "sve2p1" in {
2080+
let TargetGuard = "sve2p1|sme" in {
20812081
def SVSCLAMP : SInst<"svclamp[_{d}]", "dddd", "csil", MergeNone, "aarch64_sve_sclamp", [], []>;
20822082
def SVUCLAMP : SInst<"svclamp[_{d}]", "dddd", "UcUsUiUl", MergeNone, "aarch64_sve_uclamp", [], []>;
20832083

2084-
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
2084+
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUlbhfd", "aarch64_sve_revd">;
20852085
}
20862086

20872087
let TargetGuard = "sve2p1|sme2" in {

‎clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c

Lines changed: 196 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,15 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
22
// REQUIRES: aarch64-registered-target
33
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
4-
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
4+
// RUN: -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
55
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu \
66
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
77
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu \
88
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
99
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu \
1010
// RUN: -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
11-
11+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -target-feature +bf16 -S -disable-O0-optnone -Werror -o /dev/null %s
12+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -disable-O0-optnone -Werror -o /dev/null %s
1213
#include <arm_sve.h>
1314

1415
#ifdef SVE_OVERLOADED_FORMS
@@ -388,3 +389,196 @@ svuint32_t test_svrevd_u32_x(svbool_t pg, svuint32_t op) {
388389
svuint64_t test_svrevd_u64_x(svbool_t pg, svuint64_t op) {
389390
return SVE_ACLE_FUNC(svrevd, _u64, _x, )(pg, op);
390391
}
392+
393+
394+
// CHECK-LABEL: @test_svrevd_bf16_z(
395+
// CHECK-NEXT: entry:
396+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
397+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.revd.nxv8bf16(<vscale x 8 x bfloat> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
398+
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]
399+
//
400+
// CPP-CHECK-LABEL: @_Z18test_svrevd_bf16_zu10__SVBool_tu14__SVBfloat16_t(
401+
// CPP-CHECK-NEXT: entry:
402+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
403+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.revd.nxv8bf16(<vscale x 8 x bfloat> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
404+
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]
405+
//
406+
svbfloat16_t test_svrevd_bf16_z(svbool_t pg, svbfloat16_t op) {
407+
return SVE_ACLE_FUNC(svrevd, _bf16, _z, )(pg, op);
408+
}
409+
410+
// CHECK-LABEL: @test_svrevd_f16_z(
411+
// CHECK-NEXT: entry:
412+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
413+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.revd.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
414+
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
415+
//
416+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f16_zu10__SVBool_tu13__SVFloat16_t(
417+
// CPP-CHECK-NEXT: entry:
418+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
419+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.revd.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
420+
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
421+
//
422+
svfloat16_t test_svrevd_f16_z(svbool_t pg, svfloat16_t op) {
423+
return SVE_ACLE_FUNC(svrevd, _f16, _z, )(pg, op);
424+
}
425+
426+
// CHECK-LABEL: @test_svrevd_f32_z(
427+
// CHECK-NEXT: entry:
428+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
429+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.revd.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
430+
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
431+
//
432+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f32_zu10__SVBool_tu13__SVFloat32_t(
433+
// CPP-CHECK-NEXT: entry:
434+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
435+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.revd.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
436+
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
437+
//
438+
svfloat32_t test_svrevd_f32_z(svbool_t pg, svfloat32_t op) {
439+
return SVE_ACLE_FUNC(svrevd, _f32, _z, )(pg, op);
440+
}
441+
442+
// CHECK-LABEL: @test_svrevd_f64_z(
443+
// CHECK-NEXT: entry:
444+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
445+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.revd.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
446+
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
447+
//
448+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f64_zu10__SVBool_tu13__SVFloat64_t(
449+
// CPP-CHECK-NEXT: entry:
450+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
451+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.revd.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
452+
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
453+
//
454+
svfloat64_t test_svrevd_f64_z(svbool_t pg, svfloat64_t op) {
455+
return SVE_ACLE_FUNC(svrevd, _f64, _z, )(pg, op);
456+
}
457+
458+
// CHECK-LABEL: @test_svrevd_bf16_m(
459+
// CHECK-NEXT: entry:
460+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
461+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.revd.nxv8bf16(<vscale x 8 x bfloat> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
462+
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]
463+
//
464+
// CPP-CHECK-LABEL: @_Z18test_svrevd_bf16_mu14__SVBfloat16_tu10__SVBool_tS_(
465+
// CPP-CHECK-NEXT: entry:
466+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
467+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.revd.nxv8bf16(<vscale x 8 x bfloat> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
468+
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]
469+
//
470+
svbfloat16_t test_svrevd_bf16_m(svbfloat16_t inactive, svbool_t pg, svbfloat16_t op) {
471+
return SVE_ACLE_FUNC(svrevd, _bf16, _m, )(inactive, pg, op);
472+
}
473+
474+
// CHECK-LABEL: @test_svrevd_f16_m(
475+
// CHECK-NEXT: entry:
476+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
477+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.revd.nxv8f16(<vscale x 8 x half> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
478+
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
479+
//
480+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f16_mu13__SVFloat16_tu10__SVBool_tS_(
481+
// CPP-CHECK-NEXT: entry:
482+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
483+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.revd.nxv8f16(<vscale x 8 x half> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
484+
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
485+
//
486+
svfloat16_t test_svrevd_f16_m(svfloat16_t inactive, svbool_t pg, svfloat16_t op) {
487+
return SVE_ACLE_FUNC(svrevd, _f16, _m, )(inactive, pg, op);
488+
}
489+
490+
// CHECK-LABEL: @test_svrevd_f32_m(
491+
// CHECK-NEXT: entry:
492+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
493+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.revd.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
494+
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
495+
//
496+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f32_mu13__SVFloat32_tu10__SVBool_tS_(
497+
// CPP-CHECK-NEXT: entry:
498+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
499+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.revd.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
500+
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
501+
//
502+
svfloat32_t test_svrevd_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op) {
503+
return SVE_ACLE_FUNC(svrevd, _f32, _m, )(inactive, pg, op);
504+
}
505+
506+
// CHECK-LABEL: @test_svrevd_f64_m(
507+
// CHECK-NEXT: entry:
508+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
509+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.revd.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
510+
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
511+
//
512+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f64_mu13__SVFloat64_tu10__SVBool_tS_(
513+
// CPP-CHECK-NEXT: entry:
514+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
515+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.revd.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
516+
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
517+
//
518+
svfloat64_t test_svrevd_f64_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op) {
519+
return SVE_ACLE_FUNC(svrevd, _f64, _m, )(inactive, pg, op);
520+
}
521+
522+
// CHECK-LABEL: @test_svrevd_bf16_x(
523+
// CHECK-NEXT: entry:
524+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
525+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.revd.nxv8bf16(<vscale x 8 x bfloat> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
526+
// CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]
527+
//
528+
// CPP-CHECK-LABEL: @_Z18test_svrevd_bf16_xu10__SVBool_tu14__SVBfloat16_t(
529+
// CPP-CHECK-NEXT: entry:
530+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
531+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.revd.nxv8bf16(<vscale x 8 x bfloat> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
532+
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP1]]
533+
//
534+
svbfloat16_t test_svrevd_bf16_x(svbool_t pg, svbfloat16_t op) {
535+
return SVE_ACLE_FUNC(svrevd, _bf16, _x, )(pg, op);
536+
}
537+
538+
// CHECK-LABEL: @test_svrevd_f16_x(
539+
// CHECK-NEXT: entry:
540+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
541+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.revd.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
542+
// CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
543+
//
544+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f16_xu10__SVBool_tu13__SVFloat16_t(
545+
// CPP-CHECK-NEXT: entry:
546+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
547+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.revd.nxv8f16(<vscale x 8 x half> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
548+
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
549+
//
550+
svfloat16_t test_svrevd_f16_x(svbool_t pg, svfloat16_t op) {
551+
return SVE_ACLE_FUNC(svrevd, _f16, _x, )(pg, op);
552+
}
553+
554+
// CHECK-LABEL: @test_svrevd_f32_x(
555+
// CHECK-NEXT: entry:
556+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
557+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.revd.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
558+
// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
559+
//
560+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f32_xu10__SVBool_tu13__SVFloat32_t(
561+
// CPP-CHECK-NEXT: entry:
562+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
563+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.revd.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
564+
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
565+
//
566+
svfloat32_t test_svrevd_f32_x(svbool_t pg, svfloat32_t op) {
567+
return SVE_ACLE_FUNC(svrevd, _f32, _x, )(pg, op);
568+
}
569+
570+
// CHECK-LABEL: @test_svrevd_f64_x(
571+
// CHECK-NEXT: entry:
572+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
573+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.revd.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
574+
// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
575+
//
576+
// CPP-CHECK-LABEL: @_Z17test_svrevd_f64_xu10__SVBool_tu13__SVFloat64_t(
577+
// CPP-CHECK-NEXT: entry:
578+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
579+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.revd.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
580+
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
581+
//
582+
svfloat64_t test_svrevd_f64_x(svbool_t pg, svfloat64_t op) {
583+
return SVE_ACLE_FUNC(svrevd, _f64, _x, )(pg, op);
584+
}

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

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@@ -1259,6 +1259,12 @@ multiclass sve2_int_perm_revd<string asm, SDPatternOperator op> {
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def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Passthru_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Passthru_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Passthru_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME)>;
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def : SVE_1_Op_Passthru_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME)>;
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}
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class sve2_clamp<string asm, bits<2> sz, bit U, ZPRRegOp zpr_ty>

‎llvm/test/CodeGen/AArch64/sve2-intrinsics-revd.ll

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@@ -37,7 +37,48 @@ define <vscale x 2 x i64> @test_revd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 8 x bfloat> @test_revd_bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %b) {
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; CHECK-LABEL: test_revd_bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: revd z0.q, p0/m, z1.q
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.revd.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %b)
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 8 x half> @test_revd_f16(<vscale x 8 x half> %a, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b) {
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; CHECK-LABEL: test_revd_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: revd z0.q, p0/m, z1.q
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.aarch64.sve.revd.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b)
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ret <vscale x 8 x half> %res
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}
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define <vscale x 4 x float> @test_revd_f32(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
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; CHECK-LABEL: test_revd_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: revd z0.q, p0/m, z1.q
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x float> @llvm.aarch64.sve.revd.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b)
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ret <vscale x 4 x float> %res
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}
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define <vscale x 2 x double> @test_revd_f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
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; CHECK-LABEL: test_revd_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: revd z0.q, p0/m, z1.q
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x double> @llvm.aarch64.sve.revd.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b)
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ret <vscale x 2 x double> %res
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.revd.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.revd.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.revd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
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declare <vscale x 8 x bfloat> @llvm.aarch64.sve.revd.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i1>, <vscale x 8 x bfloat>)
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declare <vscale x 8 x half> @llvm.aarch64.sve.revd.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.aarch64.sve.revd.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)
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declare <vscale x 2 x double> @llvm.aarch64.sve.revd.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>)

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