Search results

[RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 145147

#145147 In llvm/llvm-project;

· tclin914 opened on Jun 21, 2025

[RISCV][NFC] Remove hasStdExtCOrZca

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 145139

#145139 In llvm/llvm-project;

· lenary opened on Jun 21, 2025

[RISCV] Remove -mattr=+no-rvc-hints

backend:RISC-V

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 145138

#145138 In llvm/llvm-project;

· topperc opened on Jun 21, 2025

[LangRef] Require that vscale be a power of two

backend:AArch64

backend:RISC-V

llvm:analysis

llvm:instcombine

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 145098

#145098 In llvm/llvm-project;

· preames opened on Jun 20, 2025

[RISCV] Large code model places integer/FP constant pool entries in .rodata and uses PC-relative accesses.

backend:RISC-V

Status: Open.

#145080 In llvm/llvm-project;

· topperc opened on Jun 20, 2025

[RISCV] Make All VType Parts Optional

backend:RISC-V

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 144971

#144971 In llvm/llvm-project;

· lenary opened on Jun 20, 2025

[RISCV] Combine (vp.splice (insert_elt poison, scalar, 0), vec, 0, mask, 1, vl) to vslide1up.

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 144871

#144871 In llvm/llvm-project;

· NexMing opened on Jun 19, 2025

[RISCV] Switch to sign-extended loads if possible in RISCVOptWInstrs

backend:RISC-V

llvm:globalisel

Status: Open (in progress).

llvm/llvm-projectnumber 144703

#144703 In llvm/llvm-project;

· asb opened on Jun 18, 2025

[feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv

backend:RISC-V

llvm:binary-utilities

mcMachine (object) codeMachine (object) code

Status: Open (in progress).

llvm/llvm-projectnumber 144620

#144620 In llvm/llvm-project;

· arjunUpatel opened on Jun 18, 2025

[AArch64] Add option -msve-streaming-vector-bits= .

backend:AArch64

backend:ARM

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

clang:driver'clang' and 'clang++' user-facing binaries. Not 'clang-cl''clang' and 'clang++' user-facing binaries. Not 'clang-cl'

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

Status: Open (in progress).

llvm/llvm-projectnumber 144611

#144611 In llvm/llvm-project;

· efriedma-quic opened on Jun 17, 2025

[RISCV] Investigation of Memory Operation Expansion Thresholds for RISC-V

backend:RISC-V

Status: Open.

#144562 In llvm/llvm-project;

· mikhailramalho opened on Jun 17, 2025

[RISCV] Enable loop vectorizer register pressure VF pruning again

backend:RISC-V

Status: Open.

#144520 In llvm/llvm-project;

· lukel97 opened on Jun 17, 2025