From 4d055df3e9e6d7c8218aff0bc72a0bf226ec80b5 Mon Sep 17 00:00:00 2001 From: "Gambarin, Stanley" Date: Thu, 29 May 2025 07:45:34 -0700 Subject: [PATCH 1/3] [GlobalISel] support lowering of G_SHUFFLEVECTOR with pointer args --- .../CodeGen/GlobalISel/LegalizerHelper.cpp | 6 +++--- .../AMDGPU/shufflevector-pointer-crash.mir | 21 +++++++++++++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 7b18a98d7f3ca..83ba71e4c9d49 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -8446,10 +8446,10 @@ LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { } } - if (DstTy.isScalar()) - MIRBuilder.buildCopy(DstReg, BuildVec[0]); - else + if (DstTy.isVector()) MIRBuilder.buildBuildVector(DstReg, BuildVec); + else + MIRBuilder.buildCopy(DstReg, BuildVec[0]); MI.eraseFromParent(); return Legalized; } diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir b/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir new file mode 100644 index 0000000000000..03b870b923454 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir @@ -0,0 +1,21 @@ +# RUN: llc -march=amdgcn -run-pass=legalizer -verify-machineinstrs %s -o - + +--- | + define i32 @test(i64 %arg) { + ret i32 0 + } +... +name: test +tracksRegLiveness: true +body: | + bb.0: + %9:_(p0) = G_CONSTANT i64 0 + %10:_(<2 x p0>) = G_BUILD_VECTOR %9:_(p0), %9:_(p0) + %8:_(<2 x p0>) = G_LOAD %9:_(p0) :: (load (<2 x p0>) from `ptr null`, align 64) + %11:_(p0) = G_SHUFFLE_VECTOR %8:_(<2 x p0>), %10:_, shufflemask(0) + %12:_(s32), %13:_(s32) = G_UNMERGE_VALUES %11:_(p0) + $vgpr0 = COPY %12:_(s32) + $vgpr1 = COPY %13:_(s32) + SI_RETURN implicit $vgpr0, implicit $vgpr1 +... + From a7c31d78e2a3fde8b815762a466fd3dbf5014c35 Mon Sep 17 00:00:00 2001 From: "Gambarin, Stanley" Date: Thu, 29 May 2025 14:27:19 -0700 Subject: [PATCH 2/3] fix recommendations --- .../AMDGPU/shufflevector-pointer-crash.mir | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir b/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir index 03b870b923454..ae65ef5fbaf4a 100644 --- a/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir +++ b/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir @@ -1,21 +1,22 @@ -# RUN: llc -march=amdgcn -run-pass=legalizer -verify-machineinstrs %s -o - +# RUN: llc -march=amdgcn -run-pass=legalizer -verify-machineinstrs %s -o - --- | - define i32 @test(i64 %arg) { - ret i32 0 + define i32 @test() { + unreachable } ... +--- name: test tracksRegLiveness: true body: | bb.0: - %9:_(p0) = G_CONSTANT i64 0 - %10:_(<2 x p0>) = G_BUILD_VECTOR %9:_(p0), %9:_(p0) - %8:_(<2 x p0>) = G_LOAD %9:_(p0) :: (load (<2 x p0>) from `ptr null`, align 64) - %11:_(p0) = G_SHUFFLE_VECTOR %8:_(<2 x p0>), %10:_, shufflemask(0) - %12:_(s32), %13:_(s32) = G_UNMERGE_VALUES %11:_(p0) - $vgpr0 = COPY %12:_(s32) - $vgpr1 = COPY %13:_(s32) + %0:_(p0) = G_CONSTANT i64 0 + %1:_(<2 x p0>) = G_BUILD_VECTOR %0:_(p0), %0:_(p0) + %2:_(<2 x p0>) = G_LOAD %0:_(p0) :: (load (<2 x p0>)) + %3:_(p0) = G_SHUFFLE_VECTOR %2:_(<2 x p0>), %1:_, shufflemask(0) + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3:_(p0) + $vgpr0 = COPY %4:_(s32) + $vgpr1 = COPY %5:_(s32) SI_RETURN implicit $vgpr0, implicit $vgpr1 ... From fc4a1d3668e7d281ca917aa1d069837626d2c501 Mon Sep 17 00:00:00 2001 From: "Gambarin, Stanley" Date: Fri, 30 May 2025 08:53:02 -0700 Subject: [PATCH 3/3] update test --- .../shufflevector-pointer-crash.mir | 36 +++++++++++++++++++ .../AMDGPU/shufflevector-pointer-crash.mir | 22 ------------ 2 files changed, 36 insertions(+), 22 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir new file mode 100644 index 0000000000000..ac903adba9a47 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s + +--- +name: test +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-LABEL: name: test + ; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[C]](p0) :: (load (s32), align 16) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[C1]](p0) :: (load (s32) from unknown-address + 4) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[C2]](p0) :: (load (s32) from unknown-address + 8, align 8) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(p0) = G_CONSTANT i64 12 + ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[C3]](p0) :: (load (s32) from unknown-address + 12) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>) + ; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[BITCAST]](<2 x p0>) + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[UV]](p0) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[COPY]](p0) + ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0) + ; CHECK-NEXT: $vgpr0 = COPY [[UV2]](s32) + ; CHECK-NEXT: $vgpr1 = COPY [[UV3]](s32) + ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + %0:_(p0) = G_CONSTANT i64 0 + %1:_(<2 x p0>) = G_BUILD_VECTOR %0:_(p0), %0:_(p0) + %2:_(<2 x p0>) = G_LOAD %0:_(p0) :: (load (<2 x p0>)) + %3:_(p0) = G_SHUFFLE_VECTOR %2:_(<2 x p0>), %1:_, shufflemask(0) + %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3:_(p0) + $vgpr0 = COPY %4:_(s32) + $vgpr1 = COPY %5:_(s32) + SI_RETURN implicit $vgpr0, implicit $vgpr1 +... + diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir b/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir deleted file mode 100644 index ae65ef5fbaf4a..0000000000000 --- a/llvm/test/CodeGen/AMDGPU/shufflevector-pointer-crash.mir +++ /dev/null @@ -1,22 +0,0 @@ -# RUN: llc -march=amdgcn -run-pass=legalizer -verify-machineinstrs %s -o - - ---- | - define i32 @test() { - unreachable - } -... ---- -name: test -tracksRegLiveness: true -body: | - bb.0: - %0:_(p0) = G_CONSTANT i64 0 - %1:_(<2 x p0>) = G_BUILD_VECTOR %0:_(p0), %0:_(p0) - %2:_(<2 x p0>) = G_LOAD %0:_(p0) :: (load (<2 x p0>)) - %3:_(p0) = G_SHUFFLE_VECTOR %2:_(<2 x p0>), %1:_, shufflemask(0) - %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3:_(p0) - $vgpr0 = COPY %4:_(s32) - $vgpr1 = COPY %5:_(s32) - SI_RETURN implicit $vgpr0, implicit $vgpr1 -... -