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Merge pull request #9 from nisembedded/update_to_actual
Update repo to actual state
2 parents e03b5b5 + bf020ad commit ac492c1

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6 files changed

+17
-9
lines changed

6 files changed

+17
-9
lines changed

examples/i2c.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ fn main() -> ! {
2424
let sda = gpiob.pb9.into_open_drain_output_in_state(PinState::High);
2525
let scl = gpiob.pb8.into_open_drain_output_in_state(PinState::High);
2626

27-
let mut i2c = dp.I2C.i2c(sda, scl, Config::new(400.kHz()), &mut rcc);
27+
let mut i2c = dp.I2C1.i2c(sda, scl, Config::new(400.kHz()), &mut rcc);
2828

2929
i2c.write(0x2a, &[0x80, 0xff]).unwrap();
3030
i2c.write(0x2a, &[0x01, 0x04, 0x00, 0x00]).unwrap();

src/crc.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ impl Config {
118118
Some(BitReversal::ByWord) => 0b11,
119119
};
120120

121-
crc.init().write(|w| unsafe { w.crc_init().bits(init) });
121+
crc.init().write(|w| unsafe { w.init().bits(init) });
122122
crc.pol().write(|w| unsafe { w.bits(poly) });
123123
crc.cr().write(|w| unsafe {
124124
w.rev_in()
@@ -160,7 +160,7 @@ impl Crc {
160160
let crc = unsafe { &(*CRC::ptr()) };
161161

162162
crc.init()
163-
.write(|w| unsafe { w.crc_init().bits(initial_value) });
163+
.write(|w| unsafe { w.init().bits(initial_value) });
164164
crc.cr().modify(|_, w| w.reset().set_bit());
165165
}
166166

src/serial/usart.rs

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -184,7 +184,11 @@ where
184184
Serial<USART>: hal::serial::Write<u8>,
185185
{
186186
fn write_str(&mut self, s: &str) -> fmt::Result {
187-
let _ = s.as_bytes().iter().map(|c| block!(self.write(*c))).last();
187+
let _ = s
188+
.as_bytes()
189+
.iter()
190+
.map(|c| block!(self.write(*c)))
191+
.next_back();
188192
Ok(())
189193
}
190194
}
@@ -194,7 +198,11 @@ where
194198
Tx<USART>: hal::serial::Write<u8>,
195199
{
196200
fn write_str(&mut self, s: &str) -> fmt::Result {
197-
let _ = s.as_bytes().iter().map(|c| block!(self.write(*c))).last();
201+
let _ = s
202+
.as_bytes()
203+
.iter()
204+
.map(|c| block!(self.write(*c)))
205+
.next_back();
198206
Ok(())
199207
}
200208
}

src/timer/mod.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -257,8 +257,8 @@ macro_rules! timers_external_clocks {
257257
}
258258

259259
timers_external_clocks! {
260-
TIM1: (tim1, sms1, ece),
261-
TIM3: (tim3, sms1, ece),
260+
TIM1: (tim1, sms, ece),
261+
TIM3: (tim3, sms, ece),
262262
}
263263

264264
timers! {

src/timer/pins.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ macro_rules! trigger_pins {
6464
}
6565
};
6666

67-
tim.smcr().modify(|_, w| unsafe { w.ts1().bits(ts) });
67+
tim.smcr().modify(|_, w| unsafe { w.ts().bits(ts) });
6868

6969
Self {
7070
pin,

src/timer/qei.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ macro_rules! qei {
5050
tim.ccmr1_output().write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) });
5151

5252
// Encoder mode 2.
53-
tim.smcr().write(|w| unsafe { w.sms1().bits(0b010) });
53+
tim.smcr().write(|w| unsafe { w.sms().bits(0b010) });
5454

5555
// Enable and configure to capture on rising edge
5656
tim.ccer().write(|w| {

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