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CodeGen: Set hasSideEffects = 0 on BUNDLE
The BUNDLE itself should not have side effects, and this is a property of instructions inside the bundle. The hasProperty check already searches for any member instructions, which was pointless since it was overridden by this bit. Allows me to distinguish bundles that have side effects vs. do not in a future patch. Also fixes an unnecessary scheduling barrier in the bundle AMDGPU uses to get PC relative addresses. llvm-svn: 364984
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7 files changed

+60
-59
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7 files changed

+60
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‎llvm/include/llvm/Target/Target.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1070,7 +1070,7 @@ def BUNDLE : StandardPseudoInstruction {
10701070
let OutOperandList = (outs);
10711071
let InOperandList = (ins variable_ops);
10721072
let AsmString = "BUNDLE";
1073-
let hasSideEffects = 1;
1073+
let hasSideEffects = 0;
10741074
}
10751075
def LIFETIME_START : StandardPseudoInstruction {
10761076
let OutOperandList = (outs);

‎llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll

Lines changed: 22 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -171,20 +171,22 @@ entry:
171171

172172
; GCN-LABEL: {{^}}call_void_func_byval_struct_kernel:
173173
; GCN: s_mov_b32 s33, s7
174-
; GCN: s_add_u32 s32, s33, 0xc00{{$}}
174+
; GCN-NOT: s_add_u32 s32, s32, 0x800
175175

176-
; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
177-
; GCN-DAG: v_mov_b32_e32 [[THIRTEEN:v[0-9]+]], 13
178-
; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s33 offset:8
176+
; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
177+
; GCN: buffer_store_dword [[NINE]], off, s[0:3], s33 offset:8
178+
; GCN: v_mov_b32_e32 [[THIRTEEN:v[0-9]+]], 13
179179
; GCN: buffer_store_dword [[THIRTEEN]], off, s[0:3], s33 offset:24
180180

181181
; GCN-NOT: s_add_u32 s32, s32, 0x800
182-
183182
; GCN-DAG: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s33 offset:8
184183
; GCN-DAG: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s33 offset:12
184+
; GCN-DAG: s_add_u32 s32, s33, 0xc00{{$}}
185185
; GCN-DAG: buffer_load_dword [[LOAD2:v[0-9]+]], off, s[0:3], s33 offset:16
186186
; GCN-DAG: buffer_load_dword [[LOAD3:v[0-9]+]], off, s[0:3], s33 offset:20
187187

188+
; GCN: s_getpc_b64
189+
188190
; GCN-DAG: buffer_store_dword [[LOAD0]], off, s[0:3], s32{{$}}
189191
; GCN-DAG: buffer_store_dword [[LOAD1]], off, s[0:3], s32 offset:4
190192
; GCN-DAG: buffer_store_dword [[LOAD2]], off, s[0:3], s32 offset:8
@@ -249,24 +251,27 @@ entry:
249251
; Make sure the byval alignment is respected in the call frame setup
250252
; GCN-LABEL: {{^}}call_void_func_byval_struct_align8_kernel:
251253
; GCN: s_mov_b32 s33, s7
252-
; GCN: s_add_u32 s32, s33, 0xc00{{$}}
254+
; GCN-NOT: s_add_u32 s32, s32, 0x800
253255

254-
; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
255-
; GCN-DAG: v_mov_b32_e32 [[THIRTEEN:v[0-9]+]], 13
256-
; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s33 offset:8
256+
; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
257+
; GCN: buffer_store_dword [[NINE]], off, s[0:3], s33 offset:8
258+
; GCN: v_mov_b32_e32 [[THIRTEEN:v[0-9]+]], 13
257259
; GCN: buffer_store_dword [[THIRTEEN]], off, s[0:3], s33 offset:24
258260

261+
259262
; GCN-NOT: s_add_u32 s32, s32, 0x800
260263

261-
; GCN-DAG: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s33 offset:8
262-
; GCN-DAG: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s33 offset:12
263-
; GCN-DAG: buffer_load_dword [[LOAD2:v[0-9]+]], off, s[0:3], s33 offset:16
264-
; GCN-DAG: buffer_load_dword [[LOAD3:v[0-9]+]], off, s[0:3], s33 offset:20
264+
; GCN: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s33 offset:8
265+
; GCN: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s33 offset:12
266+
; GCN-DAG: s_add_u32 s32, s33, 0xc00{{$}}
267+
; GCN: buffer_load_dword [[LOAD2:v[0-9]+]], off, s[0:3], s33 offset:16
268+
; GCN: buffer_load_dword [[LOAD3:v[0-9]+]], off, s[0:3], s33 offset:20
269+
270+
; GCN: buffer_store_dword [[LOAD3]], off, s[0:3], s32 offset:12
271+
; GCN: buffer_store_dword [[LOAD2]], off, s[0:3], s32 offset:8
272+
; GCN: buffer_store_dword [[LOAD1]], off, s[0:3], s32 offset:4
273+
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s32{{$}}
265274

266-
; GCN-DAG: buffer_store_dword [[LOAD0]], off, s[0:3], s32{{$}}
267-
; GCN-DAG: buffer_store_dword [[LOAD1]], off, s[0:3], s32 offset:4
268-
; GCN-DAG: buffer_store_dword [[LOAD2]], off, s[0:3], s32 offset:8
269-
; GCN-DAG: buffer_store_dword [[LOAD3]], off, s[0:3], s32 offset:12
270275

271276
; GCN-DAG: buffer_load_dword [[LOAD4:v[0-9]+]], off, s[0:3], s33 offset:24
272277
; GCN-DAG: buffer_load_dword [[LOAD5:v[0-9]+]], off, s[0:3], s33 offset:28

‎llvm/test/CodeGen/AMDGPU/call-argument-types.ll

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -83,14 +83,14 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
8383

8484
; HSA: buffer_load_ubyte [[VAR:v[0-9]+]]
8585
; HSA: s_mov_b32 s32, s33
86+
; MESA-DAG: buffer_load_ubyte [[VAR:v[0-9]+]]
87+
; MESA-DAG: s_mov_b32 s32, s33{{$}}
88+
8689

8790
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
8891
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4
8992
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_signext@rel32@hi+4
9093

91-
; MESA-DAG: buffer_load_ubyte [[VAR:v[0-9]+]]
92-
; MESA-DAG: s_mov_b32 s32, s33{{$}}
93-
9494
; GCN: s_waitcnt vmcnt(0)
9595
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 1
9696
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
@@ -108,12 +108,13 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
108108
; HSA: buffer_load_ubyte v0
109109
; HSA-DAG: s_mov_b32 s32, s33{{$}}
110110

111+
; MESA: buffer_load_ubyte v0
112+
; MESA-DAG: s_mov_b32 s32, s33{{$}}
113+
111114
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
112115
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4
113116
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_zeroext@rel32@hi+4
114117

115-
; MESA: buffer_load_ubyte v0
116-
; MESA-DAG: s_mov_b32 s32, s33{{$}}
117118

118119
; GCN: s_waitcnt vmcnt(0)
119120
; GCN-NEXT: v_and_b32_e32 v0, 1, v0
@@ -770,9 +771,11 @@ entry:
770771
; GCN: buffer_store_dword v33, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
771772
; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:16
772773
; GCN: buffer_load_dword v33, off, s[0:3], s32 offset:20
774+
775+
; GCN: s_getpc_b64
776+
773777
; GCN: buffer_store_dword v33, off, s[0:3], s32 offset:4
774778
; GCN: buffer_store_dword v32, off, s[0:3], s32{{$}}
775-
; GCN: s_getpc_b64
776779
; GCN: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
777780
; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
778781
; GCN-NOT: s32
@@ -790,9 +793,9 @@ entry:
790793
; GCN: buffer_store_dword v33, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
791794
; GCN: buffer_load_dword v32, off, s[0:3], s32{{$}}
792795
; GCN: buffer_load_dword v33, off, s[0:3], s32 offset:4
796+
; GCN: s_getpc_b64
793797
; GCN: buffer_store_dword v32, off, s[0:3], s32{{$}}
794798
; GCN: buffer_store_dword v33, off, s[0:3], s32 offset:4
795-
; GCN: s_getpc_b64
796799
; GCN: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
797800
; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
798801
; GCN-NOT: s32

‎llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -130,12 +130,12 @@ define amdgpu_kernel void @test_call_void_func_void_mayclobber_v31(i32 addrspace
130130
; GCN-LABEL: {{^}}test_call_void_func_void_preserves_s33:
131131
; GCN: s_mov_b32 s33, s9
132132
; GCN: s_mov_b32 s32, s33
133-
; GCN: #ASMSTART
134-
; GCN-NEXT: ; def s33
135-
; GCN-NEXT: #ASMEND
136133
; GCN: s_getpc_b64 s[4:5]
137134
; GCN-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
138135
; GCN-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+4
136+
; GCN: #ASMSTART
137+
; GCN-NEXT: ; def s33
138+
; GCN-NEXT: #ASMEND
139139
; GCN: s_swappc_b64 s[30:31], s[4:5]
140140
; GCN: ;;#ASMSTART
141141
; GCN-NEXT: ; use s33
@@ -152,16 +152,17 @@ define amdgpu_kernel void @test_call_void_func_void_preserves_s33(i32 addrspace(
152152
; GCN-LABEL: {{^}}test_call_void_func_void_preserves_s34:
153153
; GCN: s_mov_b32 s33, s9
154154
; GCN-NOT: s34
155-
; GCN: ;;#ASMSTART
156-
; GCN-NEXT: ; def s34
157-
; GCN-NEXT: ;;#ASMEND
158-
159155
; GCN-NOT: s34
160156

161157
; GCN: s_getpc_b64 s[4:5]
162158
; GCN-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
163159
; GCN-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+4
164160

161+
; GCN-NOT: s34
162+
; GCN: ;;#ASMSTART
163+
; GCN-NEXT: ; def s34
164+
; GCN-NEXT: ;;#ASMEND
165+
165166
; GCN-NOT: s34
166167
; GCN: s_swappc_b64 s[30:31], s[4:5]
167168

@@ -181,17 +182,17 @@ define amdgpu_kernel void @test_call_void_func_void_preserves_s34(i32 addrspace(
181182
; GCN-LABEL: {{^}}test_call_void_func_void_preserves_v32:
182183
; GCN: s_mov_b32 s33, s9
183184

184-
; GCN: ;;#ASMSTART
185-
; GCN-NEXT: ; def v32
186-
; GCN-NEXT: ;;#ASMEND
187-
188185
; GCN-NOT: v32
189186
; GCN: s_getpc_b64 s[4:5]
190187
; GCN-NEXT: s_add_u32 s4, s4, external_void_func_void@rel32@lo+4
191188
; GCN-NEXT: s_addc_u32 s5, s5, external_void_func_void@rel32@hi+4
192189
; GCN-NOT: v32
193190
; GCN-DAG: s_mov_b32 s32, s33
194191

192+
; GCN: ;;#ASMSTART
193+
; GCN-NEXT: ; def v32
194+
; GCN-NEXT: ;;#ASMEND
195+
195196
; GCN: s_swappc_b64 s[30:31], s[4:5]
196197

197198
; GCN-NOT: v32

‎llvm/test/CodeGen/AMDGPU/call-waitcnt.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,16 +30,16 @@ define amdgpu_kernel void @call_memory_no_dep(i32 addrspace(1)* %ptr, i32) #0 {
3030
; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
3131
; GCN-NEXT: s_mov_b32 s33, s9
3232
; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s33
33-
; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
3433
; GCN-NEXT: v_mov_b32_e32 v2, 0
34+
; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
3535
; GCN-NEXT: s_waitcnt lgkmcnt(0)
3636
; GCN-NEXT: v_mov_b32_e32 v0, s4
3737
; GCN-NEXT: v_mov_b32_e32 v1, s5
38+
; GCN-NEXT: global_store_dword v[0:1], v2, off
39+
; GCN-NEXT: v_mov_b32_e32 v0, 0
3840
; GCN-NEXT: s_getpc_b64 s[6:7]
3941
; GCN-NEXT: s_add_u32 s6, s6, func@rel32@lo+4
4042
; GCN-NEXT: s_addc_u32 s7, s7, func@rel32@hi+4
41-
; GCN-NEXT: global_store_dword v[0:1], v2, off
42-
; GCN-NEXT: v_mov_b32_e32 v0, 0
4343
; GCN-NEXT: s_mov_b32 s32, s33
4444
; GCN-NEXT: s_swappc_b64 s[30:31], s[6:7]
4545
; GCN-NEXT: s_endpgm
@@ -135,10 +135,10 @@ define void @tail_call_memory_arg_load(i32 addrspace(3)* %ptr, i32) #0 {
135135
; GCN-LABEL: tail_call_memory_arg_load:
136136
; GCN: ; %bb.0:
137137
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
138+
; GCN-NEXT: ds_read_b32 v0, v0
138139
; GCN-NEXT: s_getpc_b64 s[6:7]
139140
; GCN-NEXT: s_add_u32 s6, s6, func@rel32@lo+4
140141
; GCN-NEXT: s_addc_u32 s7, s7, func@rel32@hi+4
141-
; GCN-NEXT: ds_read_b32 v0, v0
142142
; GCN-NEXT: s_setpc_b64 s[6:7]
143143
%vgpr = load volatile i32, i32 addrspace(3)* %ptr
144144
tail call void @func(i32 %vgpr)

‎llvm/test/CodeGen/AMDGPU/sibling-call.ll

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -208,24 +208,23 @@ entry:
208208
; GCN: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1
209209
; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s5 offset:8
210210
; GCN-NEXT: s_mov_b64 exec
211+
; GCN-DAG: s_getpc_b64
211212

212213
; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Spill
213214
; GCN: buffer_store_dword v33, off, s[0:3], s5 ; 4-byte Folded Spill
214215
; GCN-DAG: v_writelane_b32 v34, s34, 0
215216
; GCN-DAG: v_writelane_b32 v34, s35, 1
216217

217-
; GCN-DAG: s_getpc_b64
218218
; GCN: s_swappc_b64
219219

220-
; GCN: s_getpc_b64 s[6:7]
221-
; GCN: s_add_u32 s6, s6, sibling_call_i32_fastcc_i32_i32@rel32@lo+4
222-
; GCN: s_addc_u32 s7, s7, sibling_call_i32_fastcc_i32_i32@rel32@hi+4
223-
224220
; GCN-DAG: v_readlane_b32 s34, v34, 0
225221
; GCN-DAG: v_readlane_b32 s35, v34, 1
226222

227223
; GCN: buffer_load_dword v33, off, s[0:3], s5 ; 4-byte Folded Reload
228224
; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:4 ; 4-byte Folded Reload
225+
; GCN: s_getpc_b64 s[6:7]
226+
; GCN: s_add_u32 s6, s6, sibling_call_i32_fastcc_i32_i32@rel32@lo+4
227+
; GCN: s_addc_u32 s7, s7, sibling_call_i32_fastcc_i32_i32@rel32@hi+4
229228
; GCN: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1
230229
; GCN-NEXT: buffer_load_dword v34, off, s[0:3], s5 offset:8
231230
; GCN-NEXT: s_mov_b64 exec

‎llvm/test/CodeGen/ARM/Windows/tls.ll

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,10 @@ define i32 @f() {
1515

1616
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
1717

18-
; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
1918
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
2019
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
2120
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
22-
21+
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
2322
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
2423

2524
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
@@ -36,11 +35,10 @@ define i32 @e() {
3635

3736
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
3837

39-
; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
4038
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
4139
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
4240
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
43-
41+
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
4442
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
4543

4644
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
@@ -57,11 +55,10 @@ define i32 @d() {
5755

5856
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
5957

60-
; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
6158
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
6259
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
6360
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
64-
61+
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
6562
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
6663

6764
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
@@ -78,11 +75,10 @@ define i32 @c() {
7875

7976
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
8077

81-
; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
8278
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
8379
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
8480
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
85-
81+
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
8682
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
8783

8884
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
@@ -99,11 +95,10 @@ define i32 @b() {
9995

10096
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
10197

102-
; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
10398
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
10499
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
105100
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
106-
101+
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
107102
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
108103

109104
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
@@ -120,11 +115,10 @@ define i16 @a() {
120115

121116
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
122117

123-
; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
124118
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
125119
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
126120
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
127-
121+
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
128122
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
129123

130124
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
@@ -141,11 +135,10 @@ define i8 @Z() {
141135

142136
; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
143137

144-
; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
145138
; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
146139
; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
147140
; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
148-
141+
; CHECK-NEXT: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
149142
; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
150143

151144
; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]

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