Labels
Labels
52 labels
- Odin II Logic Synthesis Tool: AST related phase (folding, optimization, scope, unrolling))
- Odin II Logic Synthesis Tool: Elaboration from an AST to a high level RTL netlist related phase
- Odin II Logic Synthesis Tool: Verilog Preproc and Parser related
- Odin II Logic Synthesis Tool: regression test related
- Odin II Logic Synthesis Tool: Simulation related
- Odin II Logic Synthesis Tool: Technology Mapping High level contruct into hard or soft logic
- Pull requests that update Python code
- Regression against previous behaviour
- Utility & Infrastructure scripts
- Pull requests that update Submodules code
- Tatum timing analyzer
- The Titan benchmarks: www.eecg.utoronto.ca/~kmurray/titan
- VPR FPGA Placement & Routing Tool
- The VTR verilog benchmarks included with the VTR Flow
- VTR Design Flow (scripts/benchmarks/architectures)
- Yosys synthesizer and its interaction with VTR
- The Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flow