RISC-V Demo Windows Support 2024 #56
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jennifermah76
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Feb 5, 2024
jennifermah76
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- Edit tcl scripts to support Windows by removing bash calls
- Add a .bat version of all .sh scripts
- Removed mention of Cygwin in Readme.md & Readme-compile.md
risc-v-demo/sev-kit-reference-design/script_support/additional_configurations/functions.tcl
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| REM E.g.: | ||
| REM cd sev-kit-reference-design/script_support/additional_configurations/smarthls/hls_pipeline | ||
| REM datapath=fpga arch=riscv_64 compile_and_copy.sh | ||
| REM datapath=cpu arch=riscv_64 compile_and_copy.sh |
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Shouldn't this use the Windows calling convention instead of Linux?
"CALL compile_and_copy.bat fpga riscv_64"
"CALL compile_and_copy.bat cpu riscv_64"
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Resolved: efc3614
| CALL libero.exe SCRIPT:MPFS_SEV_KIT_REFERENCE_DESIGN.tcl "SCRIPT_ARGS:%target%" logfile:partial_out.txt | ||
| echo "------[ Identify ]--------" | ||
| pushd "./SEVPFSOC_H264/synthesis/" | ||
| synplify_pro.exe -licensetype synplifypro_actel -batch ..\..\script_support\additional_configurations\smarthls\synplify_enable_dbg_mode.tcl |
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Why is Libero called with CALL but not synplify_pro?
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Resolved: efc3614
ManuelSaldana
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Feb 20, 2024
ManuelSaldana
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Jul 3, 2024
* Revert "Merge dev to main for release 2023.2" * Revert "Revert "Merge dev to main for release 2023.2"" * Added risc-v example * Add '-D__STDC_FORMAT_MACROS' to USER_CXX_FLAG of axi_target test * Fixed synthesis error for 2024_1 release On Training3 some calculations were performed during the formal port assignment or a module, potentially generating a wider bus than the actual port definition. Now the calculation is done in a separate wire assignment that performs an automatic cast to the width of the wire to prevent the mismatch. Probably Synplify got more strict about this kind of implicit type casting during formal port assignment compared to the previous version. * RISC-V Demo Windows Support 2024 (#56) - Edit tcl scripts to support Windows by removing bash calls - Add a .bat version of all .sh scripts - Removed mention of Cygwin in Readme.md & Readme-compile.md * SmartHLS 2024.1 Changes (#57) - Trainings are no longer PDFs, instead markdown files - Added bat versions of bash scripts since Cygwin is no longer used - Pre-generated Libero projects no longer used, users expected to generate projects themselves - Modified libero_flow.tcl so that if the argument GENERATE_ONLY:1 is passed in, Libero will only generate the project (i.e. not run synthesis & PnR) - Pre-compiled binaries (e.g. *job files, *elf files) to be stored in the release assets (versus in AEM) - Removed section numbers & ToC - Images & resource reports updated for 2024.1 * Fixed doc links to point to new SHLS documentation (#58) * Update readme.md (#59) Fixed incorrect .job filename * Canny RISCV Demo (#60) Added Canny_RISCV example, which shows how to use the Canny module in the SoC flow targeting the IcicleKit board. Added a readme for the example. * Update User Guide Links (#61) * Change all possible temp links to permalinks * Updated version number of User Guide links for links that do not yet have a permalink * Fixed incorrect path returned by getHLSPaths function. (#62) * Fixed incorrect path returned by getHLSPaths function. The base_path was being set incorrectly when the shls_path variable was already set by using the 'which' command. * Added fix for getting the base_path when using a release version of SHLS (#63) This fix doesn't work if the "shls" env var isn't in the path (line 21). The change to risc-v-demo/sev-kit-reference-design/script_support/additional_configurations/smarthls/sd_add_axis_converters.tcl means that "base_path" needs to be one level up from bin. So then that means "base_path" should be Libero_SoC_v2024.1/SmartHLS-2024.1/SmartHLS or C:\Microchip\Libero_SoC_v2024.1\SmartHLS-2024.1\SmartHLS. --------- Co-authored-by: jennifermah76 <132939922+jennifermah76@users.noreply.github.com> * Change name="LegUp" to name="SmartHLS" in all IDE-generated files * Revert "Change name="LegUp" to name="SmartHLS" in all IDE-generated files" --------- Co-authored-by: Duc Tran <116020996+duc-tran-mchp@users.noreply.github.com> Co-authored-by: Shuran Xu <138252634+ShuranXuMCHP@users.noreply.github.com> Co-authored-by: Manuel Saldana <manuel.saldana@microchip.com> Co-authored-by: Alireza-Mellat <100634137+Alireza-Mellat@users.noreply.github.com> Co-authored-by: Linda Mong <linda.mong@microchip.com> Co-authored-by: LindaMongMCHP <115262910+LindaMongMCHP@users.noreply.github.com> Co-authored-by: ManuelSaldana <105314255+ManuelSaldana@users.noreply.github.com> Co-authored-by: jennifermah76 <132939922+jennifermah76@users.noreply.github.com>
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