Typo fixes

Training1/readme.md

@@ -514,7 +514,7 @@ directions below.
     looking for Eclipse “.project” files in the subdirectories. Click
     Finish to import.
 
-<p align="center">="center"><img src=".//media/image32.png" /></p></br>
+<p align="center"><img src=".//media/image32.png" /></p></br>
 
 7.  After importing you should see all 9 projects in the Project
     Explorer on the left.
@@ -1747,7 +1747,7 @@ is presented in Figure 20.
 void functional_unit_contention( volatile int array[N] ) {
 #pragma HLS loop unroll factor(1)
 #pragma HLS loop pipeline
-    for (int I = 0; i < N; i++) {
+    for (int i = 0; i < N; i++) {
         int mult1 = coeff1 * coeff1;
         int mult2 = coeff2 * coeff2;
         array[i] = mult1 + mult2;
@@ -3489,7 +3489,7 @@ generated Verilog Cores into Libero® SoC SmartDesign.
 3.  Launch Libero® SoC 2024.2 and open the project: “`Libero_training1/Libero_training1.prjx`”
 
 4.  Navigate to the Design Hierarchy and search for “canny”. Right click
-    the canny_top design component and select Delete. This is to make
+    the canny_top design component and select Unlink. This is to make
     sure there are no duplicated blocks before importing the new
     canny_top HDL+ block from SmartHLS.
     <p align="center"><img src=".//media/image139.png"></p></br>
@@ -3520,10 +3520,10 @@ generated Verilog Cores into Libero® SoC SmartDesign.
     the SmartDesign toolbar for `LegUp_Image_Filters` and each parent
     component (`video_pipelining`, `VIDEO_KIT_TOP`).
 
-10. Go to the Design Flow tab and double click Generate FPGA Array Data.
+10.  Go to the Design Flow tab and double click Generate FPGA Array Data.
     This should take 1-2h to finish running.
 
-11. The Mi-V soft processor receives configuration from the Video
+11.  The Mi-V soft processor receives configuration from the Video
     Control GUI running on the PC via the USB-UART. The Mi-V uses this
     configuration to control the Image/Video Processing block. To
     program the executable that runs on the Mi-V, double click

Training2/readme.md

@@ -569,7 +569,7 @@ performance.
 18      if (!done) {
 19  // Pipeline for extra performance.
 20  #pragma HLS loop pipeline
-21        for (int I = 0; i < 100; i++)
+21        for (int i = 0; i < 100; i++)
 22          buf[i] = input_fifo.read();
 23        done = true;
 24      }
@@ -585,7 +585,7 @@ performance.
 34  // Pipeline for extra performance.
 35  #pragma HLS loop pipeline
 36        for (int i = 0; i < 100; i++)
-37          sum += buf[i\];
+37          sum += buf[i];
 38        done = false;
 39        output_fifo.write(sum);
 40      }

Training3/readme.md

@@ -1745,7 +1745,7 @@ Libero SoC 2024.2:
     navigating to and clicking
     `Training3/Libero/Libero_training3/Libero_training3.prjx`.
 2.  Navigate to the Design Hierarchy and search for “`wide_mult`”. Right
-    click the `wide_mult_axi_top` design component and select Delete.
+    click the `wide_mult_axi_top` design component and select Unlink.
     We want to avoid any duplicate blocks when importing the new wide
     multiply design from SmartHLS.