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[SYCL][FPGA] Restore legacy debug info version for the hardware #3991

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Jun 29, 2021
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[SYCL][FPGA] Restore legacy debug info version for the hardware #3991

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[SYCL][FPGA] Restore legacy debug info version for the hardware
MrSidims Jun 24, 2021
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MrSidims Jun 25, 2021
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31 changes: 13 additions & 18 deletions clang/lib/Driver/ToolChains/Clang.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8601,7 +8601,11 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
TranslatorArgs.push_back(Output.getFilename());
if (getToolChain().getTriple().isSYCLDeviceEnvironment()) {
TranslatorArgs.push_back("-spirv-max-version=1.3");
TranslatorArgs.push_back("-spirv-debug-info-version=ocl-100");
// TODO: align debug info for FPGA H/W when its SPIR-V consumer is ready
if (C.getDriver().isFPGAEmulationMode())
TranslatorArgs.push_back("-spirv-debug-info-version=ocl-100");
else
TranslatorArgs.push_back("-spirv-debug-info-version=legacy");
// Prevent crash in the translator if input IR contains DIExpression
// operations which don't have mapping to OpenCL.DebugInfo.100 spec.
TranslatorArgs.push_back("-spirv-allow-extra-diexpressions");
Expand Down Expand Up @@ -8631,23 +8635,14 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
",+SPV_INTEL_fpga_cluster_attributes,+SPV_INTEL_loop_fuse"
",+SPV_INTEL_long_constant_composite";
ExtArg = ExtArg + DefaultExtArg + INTELExtArg;
if (getToolChain().getTriple().getSubArch() ==
llvm::Triple::SPIRSubArch_fpga) {
for (auto *A : TCArgs) {
if (A->getOption().matches(options::OPT_Xs_separate) ||
A->getOption().matches(options::OPT_Xs)) {
StringRef ArgString(A->getValue());
// Enable SPV_INTEL_usm_storage_classes only for FPGA hardware,
// since it adds new storage classes that represent global_device and
// global_host address spaces, which are not supported for all
// targets. With the extension disabled the storage classes will be
// lowered to CrossWorkgroup storage class that is mapped to just
// global address space.
if (ArgString == "hardware" || ArgString == "simulation")
ExtArg += ",+SPV_INTEL_usm_storage_classes";
}
}
}
if (!C.getDriver().isFPGAEmulationMode())
// Enable SPV_INTEL_usm_storage_classes only for FPGA hardware,
// since it adds new storage classes that represent global_device and
// global_host address spaces, which are not supported for all
// targets. With the extension disabled the storage classes will be
// lowered to CrossWorkgroup storage class that is mapped to just
// global address space.
ExtArg += ",+SPV_INTEL_usm_storage_classes";
TranslatorArgs.push_back(TCArgs.MakeArgString(ExtArg));
}
for (auto I : Inputs) {
Expand Down
5 changes: 4 additions & 1 deletion clang/lib/Driver/ToolChains/SYCL.cpp
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Expand Up @@ -66,7 +66,10 @@ const char *SYCL::Linker::constructLLVMSpirvCommand(
} else {
CmdArgs.push_back("-spirv-max-version=1.3");
CmdArgs.push_back("-spirv-ext=+all");
CmdArgs.push_back("-spirv-debug-info-version=ocl-100");
if (!C.getDriver().isFPGAEmulationMode())
CmdArgs.push_back("-spirv-debug-info-version=legacy");
else
CmdArgs.push_back("-spirv-debug-info-version=ocl-100");
CmdArgs.push_back("-spirv-allow-extra-diexpressions");
CmdArgs.push_back("-spirv-allow-unknown-intrinsics=llvm.genx.");
CmdArgs.push_back("-o");
Expand Down
3 changes: 2 additions & 1 deletion clang/test/Driver/sycl-offload.c
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Expand Up @@ -693,7 +693,8 @@
// CHK-TOOLS-AOT: file-table-tform{{.*}} "-extract=Code" "-drop_titles" "-o" "[[OUTPUT2_1:.+\.txt]]" "[[OUTPUT2_T]]"
// CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
// CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
// CHK-TOOLS-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
// CHK-TOOLS-FPGA-HW: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=legacy" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
// CHK-TOOLS-FPGA-EMU: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]"
// CHK-TOOLS-FPGA-HW: aoc{{.*}} "-o" "[[OUTPUT4_T:.+\.aocx]]" "[[OUTPUT3_T]]"
// CHK-TOOLS-FPGA-EMU: opencl-aot{{.*}} "-spv=[[OUTPUT3_T]]" "-ir=[[OUTPUT4_T:.+\.aocx]]"
// CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4_T:.+\.out]]" {{.*}} "[[OUTPUT3_T]]"
Expand Down