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[CodeGen] Introduce a VirtRegOrUnit class to hold virtual reg or physical reg unit. NFC #123768

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Merged
merged 3 commits into from
Jan 25, 2025
Merged

[CodeGen] Introduce a VirtRegOrUnit class to hold virtual reg or physical reg unit. NFC #123768

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e8becd1
[CodeGen] Introduce a RegisterUnit class to hold virtual reg or physi…
topperc Jan 21, 2025
303e9fc
Merge remote-tracking branch 'origin/main' into pr/RegisterUnit
topperc Jan 23, 2025
268ca2e
fixup! Rename to VirtRegOrUnit.
topperc Jan 23, 2025
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31 changes: 31 additions & 0 deletions llvm/include/llvm/CodeGen/Register.h
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Original file line number Diff line number Diff line change
Expand Up @@ -160,6 +160,37 @@ template <> struct DenseMapInfo<Register> {
}
};

/// Wrapper class representing a virtual register or register unit.
class VirtRegOrUnit {
unsigned VRegOrUnit;

public:
constexpr explicit VirtRegOrUnit(MCRegUnit Unit) : VRegOrUnit(Unit) {
assert(!Register::isVirtualRegister(VRegOrUnit));
}
constexpr explicit VirtRegOrUnit(Register Reg) : VRegOrUnit(Reg.id()) {
assert(Reg.isVirtual());
}
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(just an idea) Maybe it's worth deleting other constructors to prevent implicit conversions to MCRegUnit / Register?

template<typename T> VirtRegOrUnit(T) = delete;


constexpr bool isVirtualReg() const {
return Register::isVirtualRegister(VRegOrUnit);
}

constexpr MCRegUnit asMCRegUnit() const {
assert(!isVirtualReg() && "Not a register unit");
return VRegOrUnit;
}

constexpr Register asVirtualReg() const {
assert(isVirtualReg() && "Not a virtual register");
return Register(VRegOrUnit);
}

constexpr bool operator==(const VirtRegOrUnit &Other) const {
return VRegOrUnit == Other.VRegOrUnit;
}
};

} // namespace llvm

#endif // LLVM_CODEGEN_REGISTER_H
4 changes: 2 additions & 2 deletions llvm/include/llvm/CodeGen/TargetRegisterInfo.h
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Expand Up @@ -466,9 +466,9 @@ class TargetRegisterInfo : public MCRegisterInfo {
}

/// Returns true if Reg contains RegUnit.
bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
bool hasRegUnit(MCRegister Reg, MCRegUnit RegUnit) const {
for (MCRegUnit Unit : regunits(Reg))
if (Register(Unit) == RegUnit)
if (Unit == RegUnit)
return true;
return false;
}
Expand Down
31 changes: 17 additions & 14 deletions llvm/lib/CodeGen/LiveIntervals.cpp
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Expand Up @@ -1066,10 +1066,10 @@ class LiveIntervals::HMEditor {
for (LiveInterval::SubRange &S : LI.subranges()) {
if ((S.LaneMask & LaneMask).none())
continue;
updateRange(S, Reg, S.LaneMask);
updateRange(S, VirtRegOrUnit(Reg), S.LaneMask);
}
}
updateRange(LI, Reg, LaneBitmask::getNone());
updateRange(LI, VirtRegOrUnit(Reg), LaneBitmask::getNone());
// If main range has a hole and we are moving a subrange use across
// the hole updateRange() cannot properly handle it since it only
// gets the LiveRange and not the whole LiveInterval. As a result
Expand All @@ -1096,7 +1096,7 @@ class LiveIntervals::HMEditor {
// precomputed live range.
for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
if (LiveRange *LR = getRegUnitLI(Unit))
updateRange(*LR, Unit, LaneBitmask::getNone());
updateRange(*LR, VirtRegOrUnit(Unit), LaneBitmask::getNone());
}
if (hasRegMask)
updateRegMaskSlots();
Expand All @@ -1105,24 +1105,25 @@ class LiveIntervals::HMEditor {
private:
/// Update a single live range, assuming an instruction has been moved from
/// OldIdx to NewIdx.
void updateRange(LiveRange &LR, Register Reg, LaneBitmask LaneMask) {
void updateRange(LiveRange &LR, VirtRegOrUnit VRegOrUnit,
LaneBitmask LaneMask) {
if (!Updated.insert(&LR).second)
return;
LLVM_DEBUG({
dbgs() << " ";
if (Reg.isVirtual()) {
dbgs() << printReg(Reg);
if (VRegOrUnit.isVirtualReg()) {
dbgs() << printReg(VRegOrUnit.asVirtualReg());
if (LaneMask.any())
dbgs() << " L" << PrintLaneMask(LaneMask);
} else {
dbgs() << printRegUnit(Reg, &TRI);
dbgs() << printRegUnit(VRegOrUnit.asMCRegUnit(), &TRI);
}
dbgs() << ":\t" << LR << '\n';
});
if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
handleMoveDown(LR);
else
handleMoveUp(LR, Reg, LaneMask);
handleMoveUp(LR, VRegOrUnit, LaneMask);
LLVM_DEBUG(dbgs() << " -->\t" << LR << '\n');
assert(LR.verify());
}
Expand Down Expand Up @@ -1302,7 +1303,8 @@ class LiveIntervals::HMEditor {

/// Update LR to reflect an instruction has been moved upwards from OldIdx
/// to NewIdx (NewIdx < OldIdx).
void handleMoveUp(LiveRange &LR, Register Reg, LaneBitmask LaneMask) {
void handleMoveUp(LiveRange &LR, VirtRegOrUnit VRegOrUnit,
LaneBitmask LaneMask) {
LiveRange::iterator E = LR.end();
// Segment going into OldIdx.
LiveRange::iterator OldIdxIn = LR.find(OldIdx.getBaseIndex());
Expand All @@ -1326,7 +1328,7 @@ class LiveIntervals::HMEditor {
SlotIndex DefBeforeOldIdx
= std::max(OldIdxIn->start.getDeadSlot(),
NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));
OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, Reg, LaneMask);
OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, VRegOrUnit, LaneMask);

// Did we have a Def at OldIdx? If not we are done now.
OldIdxOut = std::next(OldIdxIn);
Expand Down Expand Up @@ -1484,11 +1486,12 @@ class LiveIntervals::HMEditor {
}

// Return the last use of reg between NewIdx and OldIdx.
SlotIndex findLastUseBefore(SlotIndex Before, Register Reg,
SlotIndex findLastUseBefore(SlotIndex Before, VirtRegOrUnit VRegOrUnit,
LaneBitmask LaneMask) {
if (Reg.isVirtual()) {
if (VRegOrUnit.isVirtualReg()) {
SlotIndex LastUse = Before;
for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
for (MachineOperand &MO :
MRI.use_nodbg_operands(VRegOrUnit.asVirtualReg())) {
if (MO.isUndef())
continue;
unsigned SubReg = MO.getSubReg();
Expand Down Expand Up @@ -1531,7 +1534,7 @@ class LiveIntervals::HMEditor {
// Check if MII uses Reg.
for (MIBundleOperands MO(*MII); MO.isValid(); ++MO)
if (MO->isReg() && !MO->isUndef() && MO->getReg().isPhysical() &&
TRI.hasRegUnit(MO->getReg(), Reg))
TRI.hasRegUnit(MO->getReg(), VRegOrUnit.asMCRegUnit()))
return Idx.getRegSlot();
}
// Didn't reach Before. It must be the first instruction in the block.
Expand Down
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