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[Target] Use llvm::append_range (NFC) #135568

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Merged
merged 1 commit into from
Apr 13, 2025
Merged

[Target] Use llvm::append_range (NFC) #135568

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3980,7 +3980,7 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
}

if (!InsertBeforeLR)
CSI.insert(CSI.end(), VGSaves.begin(), VGSaves.end());
llvm::append_range(CSI, VGSaves);
}

Register LastReg = 0;
Expand Down
7 changes: 3 additions & 4 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -4055,8 +4055,7 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
}

if (IsChainCallConv)
Ops.insert(Ops.end(), ChainCallSpecialArgs.begin(),
ChainCallSpecialArgs.end());
llvm::append_range(Ops, ChainCallSpecialArgs);

// Add argument registers to the end of the list so that they are known live
// into the call.
Expand Down Expand Up @@ -15526,9 +15525,9 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,

// Adjust the writemask in the node
SmallVector<SDValue, 12> Ops;
Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
llvm::append_range(Ops, Node->ops().take_front(DmaskIdx));
Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
llvm::append_range(Ops, Node->ops().drop_front(DmaskIdx + 1));

MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT();

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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
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Expand Up @@ -14,6 +14,7 @@
#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H
#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H

#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include <cstddef>
#include <cstdint>
Expand Down Expand Up @@ -60,7 +61,7 @@ class UnwindOpcodeAssembler {

/// Emit unwind raw opcodes
void EmitRaw(const SmallVectorImpl<uint8_t> &Opcodes) {
Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end());
llvm::append_range(Ops, Opcodes);
OpBegins.push_back(OpBegins.back() + Opcodes.size());
}

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5 changes: 2 additions & 3 deletions llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
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Expand Up @@ -55,7 +55,7 @@ void WebAssemblyAsmTypeCheck::funcDecl(const wasm::WasmSignature &Sig) {

void WebAssemblyAsmTypeCheck::localDecl(
const SmallVectorImpl<wasm::ValType> &Locals) {
LocalTypes.insert(LocalTypes.end(), Locals.begin(), Locals.end());
llvm::append_range(LocalTypes, Locals);
}

void WebAssemblyAsmTypeCheck::dumpTypeStack(Twine Msg) {
Expand Down Expand Up @@ -357,8 +357,7 @@ bool WebAssemblyAsmTypeCheck::checkTryTable(SMLoc ErrorLoc,
Opcode == wasm::WASM_OPCODE_CATCH_REF) {
if (!getSignature(ErrorLoc, Inst.getOperand(OpIdx++),
wasm::WASM_SYMBOL_TYPE_TAG, Sig))
SentTypes.insert(SentTypes.end(), Sig->Params.begin(),
Sig->Params.end());
llvm::append_range(SentTypes, Sig->Params);
else
Error = true;
}
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