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[llvm][ARM] Emit MVE .arch_extension after .fpu directive if it does not include MVE features #71545

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Merged
merged 6 commits into from
Nov 22, 2023
Merged

[llvm][ARM] Emit MVE .arch_extension after .fpu directive if it does not include MVE features #71545

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e2b6fa1
[ARM] .fpu equals fpv5-d16 disables floating point MVE which leads to…
Nov 7, 2023
951537d
fixup! [llvm][ARM] Emit MVE .arch_extension after .fpu directive if i…
Nov 9, 2023
38c3ee0
fixup! [ARM] .fpu equals fpv5-d16 disables floating point MVE which l…
Nov 15, 2023
e8bf45c
fixup! [ARM] .fpu equals fpv5-d16 disables floating point MVE which l…
Nov 15, 2023
891c77b
fixup! [ARM] .fpu equals fpv5-d16 disables floating point MVE which l…
Nov 16, 2023
5b261a8
fixup! [ARM] .fpu equals fpv5-d16 disables floating point MVE which l…
Nov 20, 2023
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3 changes: 3 additions & 0 deletions llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12648,6 +12648,9 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name, SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
{(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
{Feature_HasV8Bit},
{ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8}},
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16 changes: 10 additions & 6 deletions llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -238,14 +238,18 @@ void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
? ARMBuildAttrs::AllowNeonARMv8_1a
: ARMBuildAttrs::AllowNeonARMv8);
} else {
if (STI.hasFeature(ARM::FeatureFPARMv8_D16_SP))
if (STI.hasFeature(ARM::FeatureFPARMv8_D16_SP)) {
// FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
// FPU, but there are two different names for it depending on the CPU.
emitFPU(STI.hasFeature(ARM::FeatureD32)
? ARM::FK_FP_ARMV8
: (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16
: ARM::FK_FPV5_SP_D16));
else if (STI.hasFeature(ARM::FeatureVFP4_D16_SP))
if (STI.hasFeature(ARM::FeatureD32))
emitFPU(ARM::FK_FP_ARMV8);
else {
emitFPU(STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16
: ARM::FK_FPV5_SP_D16);
if (STI.hasFeature(ARM::HasMVEFloatOps))
emitArchExtension(ARM::AEK_SIMD | ARM::AEK_DSP | ARM::AEK_FP);
}
} else if (STI.hasFeature(ARM::FeatureVFP4_D16_SP))
emitFPU(STI.hasFeature(ARM::FeatureD32)
? ARM::FK_VFPV4
: (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_VFPV4_D16
Expand Down
14 changes: 14 additions & 0 deletions llvm/test/CodeGen/ARM/arm-v8.1m-check-mve-extension.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
; RUN: llc -mtriple=arm-none-eabi -mcpu=cortex-m85 --float-abi=hard %s -o - | FileCheck %s
; RUN: llc -mtriple=arm-none-eabi -mcpu=cortex-m55 --float-abi=hard %s -o - | FileCheck %s

; CHECK: .fpu fpv5-d16
; CHECK-NEXT: .arch_extension mve.fp

define <4 x float> @vsubf32(<4 x float> %A, <4 x float> %B) {
; CHECK-LABEL: vsubf32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vsub.f32 q0, q0, q1
; CHECK-NEXT: bx lr
%tmp3 = fsub <4 x float> %A, %B
ret <4 x float> %tmp3
}
6 changes: 6 additions & 0 deletions llvm/test/MC/ARM/arm-v8.1m-check-mve-extension.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
// RUN: llvm-mc -triple thumbv8.1m.main-none-eabi -filetype asm -o - %s 2>&1 | FileCheck %s

.arch_extension mve.fp
vsub.f32 q0, q0, q1
// CHECK: vsub.f32 q0, q0, q1