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[RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl #81123

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Merged
merged 4 commits into from
Mar 5, 2025
Merged

[RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl #81123

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05077e9
[RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl
asb Feb 8, 2024
c700bc4
Merge remote-tracking branch 'origin/main' into 2024q1-riscv-iscopyin…
asb Mar 5, 2025
c188829
As suggested in code review, add additional isReg checks
asb Mar 5, 2025
3f40a2c
Update constbarrier-rv32.ll based on this change
asb Mar 5, 2025
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1650,6 +1650,14 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
break;
case RISCV::ADD:
if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0 &&
MI.getOperand(2).isReg())
return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
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Do we need to check that Operand 2 is a register?

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Isn't that implied by the instruction opcode? It can't be an immediate. Are you thinking a frame index or something like that?

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@topperc topperc Feb 8, 2024 •
edited
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Yes, though that's probably impossible given current FrameIndex usage. But if we want to assume that, then the isReg check before checking X0 is unneeded. So we're not consistent.

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I've added the isReg checks for the other operand for consistency.

if (MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0 &&
MI.getOperand(1).isReg())
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
break;
case RISCV::ADDI:
// Operand 1 can be a frameindex but callers expect registers
if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv32.ll
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Expand Up @@ -33,13 +33,13 @@ define void @constant_fold_barrier_i128(ptr %p) {
; RV32-NEXT: add a2, a2, a1
; RV32-NEXT: add a6, a3, zero
; RV32-NEXT: sltu a1, a2, a1
; RV32-NEXT: sltu a3, a6, a3
; RV32-NEXT: sltu a3, a3, a3
; RV32-NEXT: add a6, a6, a1
; RV32-NEXT: seqz a7, a6
; RV32-NEXT: and a1, a7, a1
; RV32-NEXT: add a7, a4, zero
; RV32-NEXT: add a5, a5, zero
; RV32-NEXT: sltu a4, a7, a4
; RV32-NEXT: sltu a4, a4, a4
; RV32-NEXT: or a1, a3, a1
; RV32-NEXT: add a7, a7, a1
; RV32-NEXT: seqz a3, a7
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10 changes: 7 additions & 3 deletions llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
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Expand Up @@ -135,7 +135,7 @@ TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
EXPECT_EQ(MI4Res->Destination->getReg(), RISCV::F1_D);
EXPECT_EQ(MI4Res->Source->getReg(), RISCV::F2_D);

// ADD. TODO: Should return true for add reg, x0 and add x0, reg.
// ADD.
MachineInstr *MI5 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
.addReg(RISCV::X2)
.addReg(RISCV::X3)
Expand All @@ -148,14 +148,18 @@ TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
.addReg(RISCV::X2)
.getInstr();
auto MI6Res = TII->isCopyInstrImpl(*MI6);
EXPECT_FALSE(MI6Res.has_value());
ASSERT_TRUE(MI6Res.has_value());
EXPECT_EQ(MI6Res->Destination->getReg(), RISCV::X1);
EXPECT_EQ(MI6Res->Source->getReg(), RISCV::X2);

MachineInstr *MI7 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
.addReg(RISCV::X2)
.addReg(RISCV::X0)
.getInstr();
auto MI7Res = TII->isCopyInstrImpl(*MI7);
EXPECT_FALSE(MI7Res.has_value());
ASSERT_TRUE(MI7Res.has_value());
EXPECT_EQ(MI7Res->Destination->getReg(), RISCV::X1);
EXPECT_EQ(MI7Res->Source->getReg(), RISCV::X2);
}

TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
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