bit-error-rate

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sascha-kirch / Bit_Error_Tester

This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.

fpga verilog prbs-generator pll bit-error-rate clock-generator

Updated Jun 2, 2022
Verilog

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bit-error-rate

Here is 1 public repository matching this topic...

sascha-kirch / Bit_Error_Tester

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