Opensource DDR3 Controller
-
Updated
Jun 14, 2025 - Verilog
Opensource DDR3 Controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
mirror of https://git.elphel.com/Elphel/eddr3
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
Add a description, image, and links to the ddr3 topic page so that developers can more easily learn about it.
To associate your repository with the ddr3 topic, visit your repo's landing page and select "manage topics."