Send video/audio over HDMI on an FPGA

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Virtio implementation in SystemVerilog

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.

Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.

This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques

The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL

Labs, exercises, and theory for the Computer Architecture course – Computer Science @ FAMAF (UNC)

test task from company

Pipelined ARMv8 with hazard detection and forwarding - Computer Architecture course project - Computer Science @ FAMAF (UNC)

A RISC-V Microprocessor

Simple register realisation for SystemVerilog Verification

verilog

SublimeText3 bits for Quartus, ModelSim, and VUnit Integration mirror of https://phabricator.kairohm.dev/diffusion/10/

A solution of test assignment from company

A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.

microcircuit SLG46620 CNT/DLY2/FSM0 (from dialog semiconductor company) SystemVerilog interpretation. Dataseet is: https://www.dialog-semiconductor.com/sites/default/files/slg46620r115_10282019.pdf Simulation: QuestaSim x64 ver2020.1 Needed simulation libraries: altera_primitives (build: $projectSource/verification/altera_primitives)