RISC-V five stage pipline CPU
-
Updated
Jul 26, 2019 - SystemVerilog
RISC-V five stage pipline CPU
Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.
Final project for the class "Digital Design with Verilog and SystemVerilog"
Add a description, image, and links to the risc-processor topic page so that developers can more easily learn about it.
To associate your repository with the risc-processor topic, visit your repo's landing page and select "manage topics."